Implementation of V-band power amplifier with high linearity in 90nm CMOS technology

Abstract

This study used 90-nm CMOS technology to design a power amplifier (PA) applicable to the V-band operation. The on-chip transformers play the power combination roles that were used to design the input, interstage and output impedance matching networks. To alleviate the power loss, the ground shielding technique is employed in proposed transformer. The measurement results indicated that the output power and OP 1dB achieve 13.2dBm and 11.6dBm, respectively. The gain was 10dB, the bandwidth is 20GHz, ranging from 55GHz to 75GHz, the power added efficiency was 4.1% at 60GHz, and the power dissipation was 430mW.Index Terms -90nm CMOS, on-chip transformer, power amplifier, power combination, V-band.