Improved Design for the High Gain Wideband Matrix Amplifiers Using Differential Cells and Microwave CMOS Technology

Abstract

 The M atrix Amplifier is a structure designed to increase the gain of the wideband distributed amplifiers.  A promising method for the deployment of high-speed optical systems with completely integrated transceivers by utilizing CM OSdistributed amplifiers with bandwidths of gigahertz to a few tens of gigahertz  The stable gain and excellent terminal match across a wide frequency range are the key reasons for the increased usage of distributed amplifiers.  The solution to the gain bandwidth roll-off problem is in this paper.  Decreasing the roll-off problem in which the values of the gain and BW are approximately balanced (High gain and high bandwidth).The M atrix Amplifier is a structure designed to increase the gain of the wideband distributed amplifiers. A matrix amplifier is used to improve the pass-band gain while preserving the dispersed design-wide characteristics to use the multiplicative gain mechanism. In this paper, the matrix distributed amplifier methodology is developed using differential cells instead of active amplifier cells to improve the wideband characteristics. Shunt capacitances are connected in the centerline to absorb the peaking impact at a cut-off frequency and reduce gain ripples. As an application of the ideas and concepts of matrix amplifiers, a modified step -by-step design of rows 4 and column 2 matrix amplifier is undertaken using a Quasi Differential amplifier. A M atrix differential amplifier using a shifted-second-tier structure technique is then built and tested in 0.18 µm Complementary M etal Oxide Semiconductors technology. The advantages gained from the proposed design are high gain, high bandwidth, low noise, and no need for balun circuits.The design and simulation results were achieved using ADS. The significant results show a high gain of 40 dB and a 33 GHz bandwidth. The noise figure is also 3.583, with S11, S22, and S12 being -10 dB, -10dB, and -40dB, respectively; the output power at 1-dB gain compression point is evaluated (P1dB) of +6.4 dBm, and the total DC power dissipation is 266mW. The cadence tools produced the layout design and specifications, although the chip size was 1.1mm 2 .