Improved Erasing Speed in Junctionless Flash Memory Device by ${\rm HfO}_{2}/{\rm Si}_{3}{\rm N}_{4}$ Stacked Trapping Layer

Chen, Chun-Yuan; Chang‐Liao, Kuei‐Shu; Wu, Kuen-Te; Wang, Tien-Ko

doi:10.1109/led.2013.2265599

Cited by 13 publications

(4 citation statements)

References 11 publications

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“…Because external power sources continuously decrease (<3.3 V) and conventional polysilicon floating gate-based flash memory usually adopts 15−25 V for operation, charge trap flash (CTF) memory has drawn intensive attention because of its capability to scale operation voltage. For CTF memory, metal nanocrystals (NCs), such as Au NCs, 1 Ni NCs, 2 W NCs, 3 and TiN NCs, 4 and high-permittivity (high-κ) dielectrics, such as HfO 2 5,6 ZrO 2 , 7,8 ZrON, 9 HfON, 10 HfO 2 /Al 2 O 3 , 11,12 HfO 2 /Si 3 N 4 , 13 and even pure TaN 14 and graphene, 15 have been proposed as the charge-trapping layers. Although these charge-trapping layers realize memory devices with high speed as well as good reliability, the operation voltage is larger than 10 V, and there is still room to reduce the voltage.…”

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confidence: 99%

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

Sun

Chen

Chu

et al. 2015

ACS Appl. Mater. Interfaces

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A stacked oxide semiconductor of n-type ZnO/p-type NiO with diode behavior was proposed as the novel charge-trapping layer to enable low-voltage flash memory for green electronics. The memory performance outperforms that of other devices with high κ and a nanocrystal-based charge-trapping layer in terms of a large hysteresis memory window of 2.02 V with ±3 V program/erase voltage, a high operation speed of 1.88 V threshold voltage shift by erasing at -4 V for 1 ms, negligible memory window degradation up to 10(5) operation cycles, and 16.2% charge loss after 10 years of operation at 85 °C. The promising electrical characteristics can be explained by the negative conduction band offset with respect to Si of ZnO that is beneficial to electron injection and storage, the large number of trapping sites of NiO that act as other good storage media, and most importantly the built-in electric field between n-type ZnO and p-type NiO that provides a favorable electric field for program and erase operation. The process of diode-based flash memory is fully compatible with incumbent VLSI technology, and utilization of the built-in electric field ushers in a new avenue of accomplishing green flash memory.

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confidence: 99%

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

Sun

Chen

Chu

et al. 2015

ACS Appl. Mater. Interfaces

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“…Comparatively, top contacted memory cells working at same operation voltage requires longer pulse duration to reach the same on/off ratio, and results in typical endurance lifetime ~10 4 cycles (See Supplementary Information S16). It is worth noting that the attained endurance lifetime achieved in edge contacted memory cells meet the requirement of the prevailing silicon flash memory (~10 5 cycles for SLC), [41][42][43][44] while having 2-4 orders' faster P/E speed (Extended data Figure 1, Supplementary Information Table S1). We further note that the memory after 10 5 endurance cycles still keeps long data retention over years (Extended data Figure 2 and Supplementary information S17), 45 demonstrating the robust durability of present flash memory cell.…”

Section: Robust Endurance Of Edge Contacted Flash Memorymentioning

confidence: 94%

Simultaneously Ultrafast and Super-Robust Two-dimensional Flash Memory Enabled by Phase Engineered Edge Contact

Zhai

Wang

et al. 2023

Preprint

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As the prevailing non-volatile memory (NVM), flash memory offers mass data storage at high integration density and low cost. However, due to the dilemma of ‘speed-retention-endurance’, their typical operation speed is limited ~microseconds to milliseconds for program and erase, restricting their application in scenarios with high-speed data throughput. Here, by adopting metallic 1T-LixMoS2 as edge contact, we show that ultrafast (10-100 ns) and super-robust (endurance>106 cycles, retention>10 years) memory operation can be simultaneously guaranteed in two-dimensional van der Waals heterostructure flash memory with 2H-MoS2 as semiconductor channel. The superior performance stems from the highly gate tunable Schottky barrier at the edge contact, which facilitates hot carrier injection to semiconductor channel and subsequent tunneling if compared to conventional top contact that has rich defects under metal. Our results show the promise of inventing 2D flash memory via contact engineering to further advance the prevailing flash memory technology to meet for the increasing demand of high speed and reliable data storage.

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“…As above mentioned, the discrete storage of charge trapping layer (CTL) NVM is candidate for scaling and improve reliability. [5][6][7][8][9][10][11] Our previous study developed a novel structure for Si-SiO 2 -Si 3 N 4 -SiO 2 -Si (SONOS) nonvolatile memory that can reduce device size and simplify fabrication process. Besides, the SONOS NVM not only has thinner tunnel oxide but also has good reliability.…”

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confidence: 99%

Artificial Defects in Si₃N₄Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors

Lin

Wang

Chen

et al. 2016

ECS J. Solid State Sci. Technol.

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This work presents a trench structure with n-type and p-type junctionless field-effect transistor (JL-FET) based on ultra-thin body (UTB) nonvolatile memory (NVM) devices with double stacked Si3N4 defect charge trapping layers (NN-CTLs). The n-type device exhibits excellent memory characteristics, including high program/erase (P/E) speed, good endurance (>104 cycles) and excellent (10-year) data retention at 85°C which achieve memory industry requirement. This simple double stacked Si3N4 trench JL-FET structure provides extra deep charge trapping sites in CTL, which improves the performance of JL-SONNOS NVMs for 3D NAND flash applications.

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Improved Erasing Speed in Junctionless Flash Memory Device by ${\rm HfO}_{2}/{\rm Si}_{3}{\rm N}_{4}$ Stacked Trapping Layer

Cited by 13 publications

References 11 publications

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

Simultaneously Ultrafast and Super-Robust Two-dimensional Flash Memory Enabled by Phase Engineered Edge Contact

Artificial Defects in Si₃N₄Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors

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Improved Erasing Speed in Junctionless Flash Memory Device by ${\rm HfO}_{2}/{\rm Si}_{3}{\rm N}_{4}$ Stacked Trapping Layer

Cited by 13 publications

References 11 publications

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation

Simultaneously Ultrafast and Super-Robust Two-dimensional Flash Memory Enabled by Phase Engineered Edge Contact

Artificial Defects in Si3N4Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors

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Artificial Defects in Si₃N₄Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors