Improved lagrangian relaxation-based gate size and V<sub>T</sub> assignment for very large circuits

Yella, Anitha Kumari; Sechen, Carl

doi:10.1109/prime-la.2017.7899169

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…Optimization techniques [Chan 1990] Greedy heuristic [Coudert 1996] Greedy heuristic [Chinnery and Keutzer 2005] Linear programming [Held 2009] Target slew [Liu and Hu 2010] Lagrangian relaxation [Huang, Hu and Shi 2011] Lagrangian relaxation [Ozdal, Burns and Hu 2012] Lagrangian relaxation and dynamic programming [Rahman and Sechen 2012] Lagrangian relaxation [Hu et al 2012] Sensitivity [Li et al 2012] Lagrangian relaxation and network flow [Reimann et al 2013] Simulated annealing [Livramento et al 2013] Lagrangian relaxation [Flach et al 2014] Lagrangian relaxation [Sharma et al 2015] Lagrangian relaxation Lagrangian relaxation [Yella and Sechen 2017] Lagrangian relaxation [Sharma et al 2017] Lagrangian relaxation…”

Section: Workmentioning

confidence: 99%

“…The objective in both contests was to minimize the leakage power of the circuit while meeting timing constraints. Since then, several papers addressing this problem were published [Hu et al 2012], [Li et al 2012], [Livramento et al 2013], [Flach et al 2013], [Flach et al 2013], [Sharma et al 2015], [Yella and Sechen 2017], [Sharma et al 2017].…”

Section: Introductionmentioning

confidence: 99%

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Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Placido

Reis

2019

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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The shrink of the devices sizes allows the number of transistors in the integrated circuits to grow, leading to an increase in the leakage power. The discrete gate sizing technique consists in assigning each gate of the circuit to a cell option among the implementation versions available in the cell library. It is a powerful method used in the design flow to carry out optimizations, e.g., timing violations fixing and power and/or area minimization. The Lagrangian relaxation based gate sizer proposed in [Flach et al. 2013] has the best leakage power results published so far for the 2012 ISPD Gate Sizing Contest benchmarks. However, its Lagrangian relaxation phase has some drawbacks. It requires many iterations to converge to a good solution in terms of leakage power. Also, during the initial iterations, the leakage power blows up, so a parcel of the iterations is used to reduce this peak of leakage power. Yet, the Lagrangian relaxation subproblem solver does not rely on any technique to perform cell option candidate filtering, so it can be very timing consuming. Therefore, in this work, the discrete gate sizing flow proposed in [Flach et al. 2013] is extended to tackle the drawbacks aforementioned. It is proposed some enhancements to the Lagrange multiplier update formula that enable the Lagrangian relaxation core to converge faster. It is also used a scaling factor to properly scale timing cost and leakage power when evaluating a cell candidate in the Lagrangian relaxation subproblem solver. So, the scaling factor, alongside the new Lagrange multipliers update method, controls the leakage power blow up during the initial Lagrangian relaxation iterations. Moreover, it is applied a cell option candidate filtering strategy to reduce the runtime of each Lagrangian relaxation iteration. Finally, the post-processing timing recovery and power recovery phases of the original work are improved to reduce the overall flow runtime. The new approach achieved leakage power results similar to the baseline work, taking 4.28× fewer iterations and 9.11× fewer cell option candidates evaluation, on average, in the Lagrangian relaxation phase. Also, the leakage power blow up during the initial iterations of the Lagrangian relaxation was reduced from 9.55× the final value, on average, to 2.74× the final value, on average. Finally, compared to [Sharma et al. 2017], which is the fastest gate sizing algorithm published so far, the new approach produced, without using the post-processing power recovery phase, similar leakage power results in general, performing slightly better for the largest benchmark.

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Section: Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Placido

Reis

2019

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

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Are standalone gate size and V<inf>T</inf> optimization tools useful?

Yella

Srivatsa

Sechen

2017

2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)

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Improved lagrangian relaxation-based gate size and V_T assignment for very large circuits

Cited by 2 publications

References 16 publications

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Are standalone gate size and V<inf>T</inf> optimization tools useful?

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Improved lagrangian relaxation-based gate size and VT assignment for very large circuits

Cited by 2 publications

References 16 publications

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

Are standalone gate size and V<inf>T</inf> optimization tools useful?

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Improved lagrangian relaxation-based gate size and V_T assignment for very large circuits