Improving design verifiability by early RTL coverability analysis

Abstract

Achieving high coverage is an important goal in design verification. Fixing coverability problems found at the verification stage, however, can require tremendous effort. To address this problem, we propose a flow for analyzing code and variable-toggle coverability at the early-RTL block-level stage. In addition, we devise a novel technique to analyze the coverability problems so that engineers can resolve the issues more efficiently. By identifying coverability problems at early RTL design stages, design verifiability can be improved, thus reducing the effort required at the verification phase.