Incremental re-encoding for symbolic traversal of product machines

Quer, S.; Cabodi, G.; Camurati, P.; Lavagno, L.; Sentovich, E.; Brayton, R.K.

doi:10.1109/eurdac.1996.558199

Cited by 3 publications

(1 citation statement)

References 4 publications

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“…In [10], the use of functional dependencies is proposed to exploit the relation between the state encodings of both circuits during the state-space traversal of the product machine. In [22], a method is described to incrementally re-encode one of the circuits to factor out their differences.…”

Section: Related Workmentioning

confidence: 99%

Sequential equivalence checking based on structural similarities

Eijk

2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Checking the functional equivalence of sequential circuits is an important practical problem. Because general algorithms for solving this problem require a state-space traversal of the product machine, they are computationally expensive. In this paper, we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the statespace traversal. The effectiveness of the proposed method is confirmed by experimental results on retimed and optimized ISCAS'89 benchmarks.

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Section: Related Workmentioning

confidence: 99%

Sequential equivalence checking based on structural similarities

Eijk

2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Sequential equivalence checking without state space traversal

Eijk¹

Proceedings Design, Automation and Test in Europe

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Record and play: a structural fixed point iteration for sequential circuit verification

Stoffel

Kunz²

1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

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This paper proposes a technique for sequential logic equivalence checking by a structural fured point iteration. Verification is performed by expanding the circuit into an iterative circuit array and by proving equivalence of each time frame by well-known combinational verification techni ues. circuit transformations. Starting from the initial state, for each time frame the performed circuit transformations are stored ("recorded") in an instruction queue. In subsequent time frames the instruction queue is re-used ('blayed'') and updated when necessary. At some point the instruction queue does not need to be modified any more and is valid in all subsequent time frames. Thus, a fixed point is reached and machine equivalence is proved by induction. Experimental results show the great promise of this approach to verify circuits after resynthesis and retiming.These exploit structural similarity between designs by 4 oca1

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Incremental re-encoding for symbolic traversal of product machines

Cited by 3 publications

References 4 publications

Sequential equivalence checking based on structural similarities

Sequential equivalence checking based on structural similarities

Sequential equivalence checking without state space traversal

Record and play: a structural fixed point iteration for sequential circuit verification

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