Abstract:The past decade has witnessed a tremendous reduction in the feature size from the deepsubmicron to the advanced nano-scale CMOS devices. In nanoscale devices based high-speed systems, the budgeting of jitter due to supply fluctuations is one of the major performance bottlenecks while designing integrated circuits (ICs). In this paper, an accurate and efficient method to analyse power supply induced jitter (PSIJ) in CMOS N-stage inverters is developed using the estimation-by-inspection method. Based on the Inde… Show more
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