Inductance tolerance analyses and design-process map of embedded planar spiral inductor

Abstract

Inductors can be fabricated directly on chip or on ceramic and organic substrates to enhance performance of mobile and RF devices. Inductors fabricated on chip are more precise with tighter tolerances, but are more costly. Inductors fabricated on organics are lower in cost, but have higher tolerances owing to higher tolerances in fabrication processes on organic boards. Inductance simulations and experiments were conducted in this investigation to examine the dependences of inductance on geometric factors. ,4 parametric study was conducted to investigate the effect of geometric variations on the inductance tolerance. Planar spiral inductors with different line width (1 00-400pm), coil pitch (1 00-4OOpm) and number of turns (4-8) were simulated. Selected inductor configurations were fabricated on FR4 substrates using standard patterning and etching processes. Analysis revealed that etching has a pivotal influence on inductance tolerance. On this basis, a new normalizing procedure is developed to relate the inductor s-hucture, inductance and inductance tolerance to fabrication process precision.The methodology is summarized in an inductor design-process map to facilitate the design of inductors on organic substrates and is illustrated in application case study. With the map, using standard PWB copper patterning and etching processes. The coils are placed on the top surface or laminated with other layers into multi-layered packages. Square spiral coil is the rnost commonly found structure which gives the highest inductance density. The inductance of the square spiral inductor is determined by coil geometry, which depends on number of turns (N), line width (w), pitch (p), outer diameter (do) and inner diameter (din) (Figure 3).inductors can be designed to have specific level of tolerance with less design-prototyping cycles. Process engineers can use the map to project the level of inductance tolerance achievable by their processes, which means the map can enable early integration of process issues into the electrical design of inductors. Figure 1: (a) On-chip inductors and (b) embedded inductors in LTCC package (cross-sectional view)