Informed Fixed Scheduling for Faster Convergence of Shuffled Belief-Propagation Decoding

Aslam, Chaudhry Adnan; Guan, Yong Liang; Cai, Kui; Han, Guangjie

doi:10.1109/lcomm.2016.2617309

Cited by 21 publications

(8 citation statements)

References 8 publications

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“…In simulations, ‘Semi‐serial TVDAS’ represents the proposed semi‐serial scheduling with one serial subset and three parallel subsets. For comparison, we also consider the IFS [13] and the conventional BP algorithm (flooding [9], shuffled [10], LBP [11] scheduling).…”

Section: Simulation Resultsmentioning

confidence: 99%

“… BER and FER curves versus Raw‐BER of the proposed TVDAS, flooding [ 9 ], shuffled [ 10 ], LBP [ 11 ] scheduling and IFS [ 13 ]. The (448, 4544) QC‐LDPC code is adopted as the channel code, and the maximum number of iterations is set to 10 and 50, respectively …”

Section: Simulation Resultsmentioning

confidence: 99%

“…The shuffled scheduling is based on a serial update of variable nodes' messages, while the layered scheduling is based on a serial update of check nodes' messages. Following this work, a column‐weight (CW) based fixed scheduling [12] and an informed fixed scheduling (IFS) [13] have been developed to improve the convergence of shuffled scheduling. The CW scheduling is based on a sequential update of variable‐node degree.…”

Section: Introductionmentioning

confidence: 99%

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Threshold‐voltage‐drift‐aware scheduling for belief propagation decoding of LDPC‐coded NAND flash memory

et al. 2019

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Threshold‐voltage‐drift‐aware scheduling for belief propagation decoding of LDPC‐coded NAND flash memory

et al. 2019

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“…Aslam et al 41 introduced a novel information fixed scheme for BPA‐based decoding scheduling of LDPC codes. This scheme focuses on improving the convergence rate of the conventional BPA by careful selection of reliable variable nodes.…”

Section: Belief Propagation‐based Ldpc Decoding Algorithms and Its Immentioning

confidence: 99%

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

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Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

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“…Nevertheless, the LLRBP algorithm suffers from slow convergence speed and low error-correction performance. The message updates of the SBP algorithm are given as follows [22]…”

Section: Standard Serial Scheduling For Ldpc Codesmentioning

confidence: 99%

Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory

2019

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With the fast development of non-volatile storage technology, NAND flash memory faces more and more challenges such as data reliability and lifetime. To overcome the issue of the reliability, low-density parity-check (LDPC) codes are considered as a main candidate of error-correction-codes (ECCs) for NAND flash storages. However, conventional soft decoding algorithms for LDPC codes suffer from the drawback of slow convergence speed, which increases the decoding latency. For achieving fast convergence speed, a variable-node-based belief-propagation with message pre-processing (VNBP-MP) decoding algorithm for binary LDPC codes and a non-binary VNBP-MP (NVNBP-MP) decoding algorithm for non-binary LDPC codes are proposed. Both of the algorithms utilize the characteristics of the NAND flash channel to perform the message pre-processing operations. In theory, the propagation of unreliable messages can be effectively prevented and the propagation of reliable messages can be speeded up. To further improve the decoding convergence, the treatment for oscillating variable nodes is considered after the message pre-processing operations. The simulation results also show that the proposed algorithms both have a noticeable improvement in convergence speed and latency, without compromising error-correction performance, compared with the existing soft decoding algorithms. INDEX TERMS NAND flash memory, low-density parity-check (LDPC) code, message pre-processing, belief-propagation decoding, error-correction performance.

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Informed Fixed Scheduling for Faster Convergence of Shuffled Belief-Propagation Decoding

Cited by 21 publications

References 8 publications

Threshold‐voltage‐drift‐aware scheduling for belief propagation decoding of LDPC‐coded NAND flash memory

Threshold‐voltage‐drift‐aware scheduling for belief propagation decoding of LDPC‐coded NAND flash memory

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory

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