Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields

Pradhan, Dibakar; Meher, Pramod Kumar; Meher, Bimal Kumar

doi:10.1007/s00034-024-02793-0

Circuits Syst Signal Process

2024

DOI: 10.1007/s00034-024-02793-0

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Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields

Dibakar Pradhan,

Pramod Kumar Meher,

Bimal Kumar Meher

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FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF$$(2^m)$$

Pradhan,

Meher,

Meher

2024

Circuits Syst Signal Process

View full text Add to dashboard Cite

FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF$$(2^m)$$

Pradhan,

Meher,

Meher

2024

Circuits Syst Signal Process

View full text Add to dashboard Cite

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Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields

Cited by 1 publication

References 29 publications

FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF$$(2^m)$$

FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF$$(2^m)$$

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