Integrated circuits for data transmission over twisted-pair channels

Johns, D.A.; Essig, D.

doi:10.1109/4.557638

Cited by 44 publications

(11 citation statements)

References 28 publications

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“…Figure 1(b) shows closed eye in its eye-diagram. The degraded signal of this eye at the receiver-end is mostly due to inter-symbol-interference (ISI) effect which limits the transmission speed of a system and its cable length [2]. The DDI needs long-distance, low-loss and low-cost cables with ever-increasing transmission speed.…”

Section: Introductionmentioning

confidence: 99%

8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface

Kim

Lee

Yoo

et al. 2009

Analog Integr Circ Sig Process

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This paper presents a continuous-time equalizer which provides a low-power, small area and low-cost solution for a DDI implementation. Proposed equalizer adopts clock attenuation detector, enabling one to eliminate complex-and-large feed-back loops, and to achieve compact design and low-power consumption. Using the attenuation signal to all four adaptive equalizer filters composed of three signal channels and a clock channel, one curtails three adaptive attenuation detectors in a multi-channel DDI. The design was done in 0.18-lm CMOS technology. Experimental results summarize that this equalizer can compensate up to -33 dB channel attenuation at 1.65-Gbps DDI rate, showing eye-width of 0.70 UI. Its average power consumption is 8 mW and the effective area is 0.127 mm 2 . This power consumption is very low in comparison to those of previous researches and the effective area is very small.

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Section: Introductionmentioning

confidence: 99%

8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface

Kim

Lee

Yoo

et al. 2009

Analog Integr Circ Sig Process

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“…100BASE-TX performs data transmission and receipt using two pairs of category (CAT) 5 cables, while 1000BASE-T Gigabit Ethernet uses four pairs of TP cables. In fact, CAT 5 cables are widely deployed cabling systems for highspeed LANs [3].…”

Section: Introductionmentioning

confidence: 99%

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Hong

Baek

Sunwoo

2009

J Sign Process Syst

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This paper presents a novel digital signal processing (DSP) unit including a new baseline wander (BLW) corrector to support fast Ethernet in twisted pair (TP) cable channels. The proposed DSP unit consists of a programmable gain amplifier (PGA), timing recovery loop, adaptive equalizer and the new BLW corrector. Unlike the existing BLW correctors, the proposed BLW corrector calculates the BLW error by subtracting the equalizer input from the slicer output. Moreover, the new BLW corrector implemented in the digital domain uses four symbols to remove the BLW instead of the two symbols used in previous works. In addition, the proposed adaptive equalizer uses 2 −7 as the optimum step size, i.e., μ. Since μ is a multiple of 2, the equalizer eliminates the need for multipliers and, thus, has a small area and consumes less power. To verify the performance of the proposed DSP unit, floating-point and fixed-point simulations using the SPW™ tool were performed. The measured BER is less than 10 −10 when the cable length is 150 m. The proposed DSP unit was modeled by Verilog-HDL and synthesized using the 0.18 μm SEC cell library. The implemented DSP unit having 128,528 gates can operate at 142.7 MHz.

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“…1 shows a simplified block diagram of a full-duplex baseband data transmission system. To allow simultaneous transmission and reception, a hybrid circuit (H) interfaces the two-wire channel to the transmit and receive circuits; ideally, the hybrid passes the local transmit signal onto the channel and isolates the receiver input V RX from the local transmitter output V TX [1], [2]. The receiver input V RX passes through a bandlimiting filter (Rx LPF) and a programmable-gain amplifier (PGA), which scales the ADC input so that its full input range is utilized.…”

Section: Introductionmentioning

confidence: 99%

Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver

Zhang

Hurst

Levy

et al. 2009

IEEE Trans. Circuits Syst. II

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Two approaches to calibrate a pipelined analog-todigital converter (ADC) and adapt an equalizer in a baseband receiver are proposed. Adaptive digital correction is used to calibrate the weights applied to the ADC output decisions so that the mean square error across the slicer in the receiver is minimized. Simulation results are presented to demonstrate the joint calibration of a pipelined ADC and adaptation of a channel equalizer.

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Integrated circuits for data transmission over twisted-pair channels

Cited by 44 publications

References 28 publications

8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface

8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface

Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver

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