Integration challenges of porous ultra low-k spin-on dielectrics

Mosig, K.; Jacobs, T.H.; Brennan, K.; Rasco, M.; Wolf, Josh; Augur, R.

doi:10.1016/s0167-9317(02)00767-0

Cited by 86 publications

(49 citation statements)

References 7 publications

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“…218,219 Another thermal property of significant importance for low-k DB and ILD materials is thermal conductivity. Dissipation of thermal energy produced directly in the metal interconnect is becoming a significant concern as continued dimensional and density scaling is leading to increased Joule heating resulting from the associated increases in metal line resistance and current density.…”

Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

133

115

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“…Primary ion beams are typically based on Ga or Cs, although other materials such as Xe, Ar, SF 6 , O 2 and even fullerene can be employed. The ejected secondary ions are then accelerated into a mass spectrometer, where the time to reach the detector (time-of-flight) is measured.…”

Section: Time-of-flight Secondary Ion Mass Spectrometry (Tof-sims)-tmentioning

confidence: 99%

“…However, it was also acknowledged that the convergence of increasing porosity and decreasing device feature sizes would ultimately lead to severe integration issues for dielectric insulators with k < 2.7. [3][4][5][6] The resulting structural changes in both density and networkconnectivity (as compared to SiO 2 ) negatively impacted the mechanical properties of the porous low-k materials, [7][8][9][10][11][12][13] leading in some cases to drastic failure during chip packaging.…”

mentioning

confidence: 99%

Toward Successful Integration of Porous Low-k Materials: Strategies Addressing Plasma Damage

Lionti

Volksen

Magbitang

et al. 2014

ECS J. Solid State Sci. Technol.

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The increasing sensitivity of porous low dielectric constant materials to process damage constitutes a major roadblock to their implementation in back-end-of-the-line (BEOL) wiring structures for advanced technology nodes. In the early 2000s and in anticipation to future low-k related integration challenges, the semiconductor industry started to investigate the possibility to repair or prevent this damage. It is remarkable that the most disruptive solutions proposed today are inspired from the work initiated more than 10 years ago. In this review we first describe the accepted mechanisms for plasma damage, followed by a quick summary of the methods used to quantify its extent on both blanket films and patterned structures. We then report on the past and current strategies developed to mitigate the plasma damage of porous, low-k materials during damascene integration processes.

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“…Porous dielectrics suffer from inferior mechanical (elastic modulus, prone to cracking) and electrical properties, e.g. water uptake, and as a result, integration with present CMOS based technologies is exceptionally complex [220][221]. Conversely, the advent of templated mesoporous silica films has allowed for the fabrication of low-k films with organised porosity [9].…”

Section: Low-k Dielectrics/proton Gated Devicesmentioning

confidence: 99%

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

Farrell

Petkov²,

Morris

et al. 2010

Journal of Colloid and Interface Science

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Self-assembled nanoscale porous architectures, such as mesoporous silica films (MPS), block copolymer films (BCP) and porous anodic aluminas (PAAs), are ideal hosts for templating one dimension (1 D) nano-entities for a wide range of electronic, photonic, magnetic and environmental applications. All three templates offer dimensional scalability and tunability over a wide range, with critical pore sizes for each system well below the 20 nm threshold [1][2][3]. Recently, research has progressed towards controlling the pore direction, orientation and long range order of these nanostructures through so called directed self-assembly (DSA). Significantly, the introduction of a wide range of top-down chemically and physically pre-patterning substrates has facilitated the DSA of nanostructures into functional device arrays. The following review begins with an overview of the fundamental aspects of self-assembly and ordering processes during the formation of PAAs, BCPs and MPS films. Special attention is given to the different ways of directing self-assembly, concentrating on properties such as uni-directional alignment, precision placement and registry of the self-assembled structures to hierarchal or top down architectures. Finally, to distinguish this review from other articles we focus on research where nanostructures have been utilised in part to fabricate arrays of functioning devices below the sub 50 nm threshold, by subtractive transfer and additive methods. Where possible, we attempt to compare and contrast the different templating approaches and highlight the strengths and/or limitations that will be important for their potential integration into downstream processes. ACCEPTED MANUSCRIPT 3 SECTION 1.0: SELF ASSEMBLY AND NANO-ARCHITETCURESThe diversity of self-assembled nanostructures and more importantly, their precise orientation within a thin film (fixed to a substrate) ultimately determines their function and overall application. A large population of research reports to date have focused on identifying these orientations and related periodicities, using x-ray and microscopy tools, as well the development of methods for readily manipulating nanostructures, such as pre-patterning of silicon substrates for the alignment of block copolymers (BCPs) [4] and mesoporous thin films (MTFs) [5] and altering the growth direction of porous anodic alumina (PAA) templates [6]. In this section, a brief synopsis of the mechanisms behind the self-assembly/organisation of each system and highlight nanoscale architectures (and orientations), which are important from a device perspective. Templated mesoporous thin filmsOrdered mesoporous powders were first discovered by researchers at the Mobil Petrochemical Corporation in 1992 and shortly after, sol-gel derived mesoporous silica films were fabricated [1,7].The first series of ordered mesoporous films were reported by Yang et al. in 1996 [8], prepared using initial surfactant concentrations above their critical micelle concentration (CMC). However the films prepared fil...

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Integration challenges of porous ultra low-k spin-on dielectrics

Cited by 86 publications

References 7 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Toward Successful Integration of Porous Low-k Materials: Strategies Addressing Plasma Damage

Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices

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