Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process

Mineji, A.; Tamura, Y.; Watanabe, T.; Ozaki, H.; Ootsuka, F.; Aoyama, T.; Shibata, Kouichi; Tsujita, Kosaku; Ohashi, N.; Yasuhira, M.; Arikado, T.

doi:10.1109/iedm.2004.1419334

Cited by 6 publications

(8 citation statements)

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“…After the implantation and interfacial oxide formation, HfSiO was deposited by metal-organic chemical vapor deposition (MOCVD), followed by O 3 and NH 3 treatments at 700 C for nitridation in the same chamber. 4,8) The physical thicknesses of the final HfSiON and interfacial SiO 2 are 2.5 and 0.5 nm, respectively. An ultrathin SiN layer was deposited by cyclic CVD for 10 cycles as an option after the HfSiON deposition.…”

Section: Device Fabrication and Measurementsmentioning

confidence: 99%

“…1) As one of the most promising candidates, hafnium silicon oxynitride (HfSiON) has been extensively studied and finally implemented in the 65 nm technology node and beyond because of its high carrier mobility and low gate leakage current. [2][3][4] However, the possible chemical reaction between the polycrystalline silicon (polySi) gate and the HfSiON dielectrics may lead to an undesirable threshold voltage (V th ) shift. 5) To circumvent this problem and improve the transistor performance, a cap layer insertion into HfSiON has recently been reported by using AlO x , 6) La 2 O 3 , 7) SiN, 8) or low-hafnium-concentration layer.…”

Section: Introductionmentioning

confidence: 99%

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Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

Zhu¹,

Takeue²,

Nakajima³

2010

Jpn. J. Appl. Phys.

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The negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) of HfSiON/SiO2 metal–oxide–semiconductor field-effect transistors (MOSFETs) with and without an ultrathin SiN cap layer were investigated. For the PBTI of n-channel MOSFETs, the dominant degradation mechanism is the electron tunneling from the Si channel and electron trapping in the pre-existing traps in HfSiON. The SiN cap layer does not make a significant difference in PBTI. For the NBTI of p-channel MOSFETs, on the other hand, both the electron trapping in HfSiON and the dissociation of Si–H bonds at the SiO2/channel-Si interface (i.e., the interface trap generation) play a role and the SiN cap layer makes a significant difference in NBTI: the dominant degradation mechanism for the devices without the SiN cap layer is the electron trapping in HfSiON, whereas that for the devices with the SiN cap layer is the interface trap generation. This indicates that the interfacial SiN cap layer can effectively suppress the electron tunneling from the polycrystalline silicon (polySi) gate to HfSiON under the NBT stress.

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Section: Device Fabrication and Measurementsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

Zhu¹,

Takeue²,

Nakajima³

2010

Jpn. J. Appl. Phys.

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“…Therefore, HfSiON is thought to be the most promising material for hp65 node [8][9][10][11]. Nitrogen atoms incorporated into HfSiO film effectively suppress the crystallization, phase separation, and boron penetration after high temperature source/drain activation process.…”

Section: High-k Gate Dielectrics For Hp65/45 and Beyondmentioning

confidence: 99%

“…HfSiON film has superior characteristics as a high-k gate dielectric such as high thermal stability, high carrier mobility, and tolerance to boron penetration. Therefore, HfSiON is thought to be the most promising material for hp65 node [8][9][10][11]. Nitrogen atoms incorporated into HfSiO film effectively suppress the crystallization, phase separation, and boron penetration after high temperature source/drain activation process.…”

Section: High-k Gate Dielectrics For Hp65/45 and Beyondmentioning

confidence: 99%

Front-End Process Technology for hp65/45 CMOS Devices

Nara¹,

Ootsuka²,

Nakamura³

2006

ECS Trans.

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In order to obtain high performance CMOS devices, introduction of new technologies into the front-end fabrication process are required and therefore so-called "technology boosters" such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices. In this proceeding, we will discuss on highk gate dielectrics and metal gate technology, and recent achievements of these technologies are reviewed.

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“…These issues include solving mobility degradation and threshold voltage instability, as well as reducing the number of fixed charges and charge traps [1]- [4]. Although there exist numerous literature reports regarding methods to incorporate nitrogen [5], [6] or Si [7], [8] into Hf-based films or stacks so as to improve the film's quality, however, to the best of our knowledge, the effect of F incorporation on HfO 2 gate dielectric was seldom addressed [9], [10]. In this letter, fluorine incorporation through fluorine implantation into the source/drain regions was used to evaluate its impact on the constant voltage stress (CVS) instability and negative bias temperature instability (NBTI) of pMOSFETs with HfO 2 gate stacks.…”

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confidence: 99%

Improved reliability of HfO/sub 2//SiON gate stack by fluorine incorporation

Chiein

Lan

et al. 2006

IEEE Electron Device Lett.

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Effects of fluorine (F) incorporation on the reliabilities of pMOSFETs with HfO 2 /SiON gate stacks have been studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V th , subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.Index Terms-Bias temperature instability (BTI), fluorine (F), hafnium oxide, plasma charging damage.

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Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process

Cited by 6 publications

References 0 publications

Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks

Front-End Process Technology for hp65/45 CMOS Devices

Improved reliability of HfO/sub 2//SiON gate stack by fluorine incorporation

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