IntelliSoC: A System Level Design and Conception of a System- on-a-Chip (SoC) to Cognitive Agents Architecture

Abstract

This chapter presents a system level design and conception of a System-on-a-Chip (SoC) for the execution of cognitive agents. The computational architecture of this SoC will be presented using the cognitive model of the concurrent autonomous agent (CAA) as a reference. This cognitive model comprises three levels that run concurrently, namely the reactive level, the instinctive level and the cognitive level. The reactive level executes a fast perception-action cycle. The instinctive level receives perceptions from and sends the active behavior to the reactive level, and using a Knowledge Based System (KBS) executes plans by selecting reactive behaviors. The cognitive level receives symbolic information from the instinctive level to update its logical world model, used for planning and sends new local goals to instinctive level. Thus, this work proposes a novel SoC whose architecture fits the computational demands of the aforementioned cognitive model, allowing for fast, energy-efficient, embedded intelligent applications.

System Level Design and Conception of a System-on-a-Chip (SoC) for Cognitive Robotics

“…The instinctive level uses its KBS to select the appropriate reactive behaviour to be selected given the current world state. The cognitive level, in turn, uses its KBS inside the Graphplan algorithm (that will be described later in this chapter), in the state space expansion stage [10].…”

“…The constructed graph has two portions: the alpha network, responsible for comparing the constants in the premises with the corresponding fields in the incoming fact; and the beta network, which checks for variable assignment consistency and maintenance of partial matches [10].…”

“…The TLM model proposed is shown in Figure 6. It consists of modified SystemC model of the Rete processor presented in the authors previous work ( [10]). As can be seen in Figure 6, the instinctive module now implements a detailed Rete processor, that uses two Content Addressable Memories (CAMs) to implement the knowledge base and an auxiliary stage for test execution.…”

“…The Instruction Set Architecture (ISA) of the Rete processor described in [10] is still employed in this model, but now some tasks related to join node in the Rete network are performed separately in the Join Node Module.…”