Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

Kim, Yoonjin; Joo, Hyejin; Yoon, Sohyun Kate

doi:10.1049/iet-cds.2015.0047

Cited by 6 publications

(2 citation statements)

References 18 publications

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“…Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, and Shaojun Wei [2], provides the CGRA with high performance and the loop pipelining techniques are usually used to exploit the parallelism of loops.The paper [3] discussed about the CGRA based multi core architecture achieving high performance by using kernel level parallelism. it as the high energy consumption and performance bottleneck.…”

Section: Related Workmentioning

confidence: 99%

Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture

Murali¹

2018

IJRASET

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A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units. CGRAs are a well-researched topic and the design space of a CGRA is quite large. A typical CGRA requires many processing elements and a configuration cache for reconfiguration of its processing element array. However, such a structure consumes significant area and power. Therefore, designing cost-effective CGRA has been a serious concern for reliability of CGRA-based embedded systems. Reusable Context Pipelining is a universal approach in reducing power and enhancing performance for CGRA because it can be achieved by closing the power performance gap between the low powers oriented spatial mapping and high performance oriented temporal mapping. By focusing on the processor elements the power and area will be reduced. The processing element consists of arithmetic and logic unit, array multiplier, saturation arithmetic logic and multiplexer. The above components are designed for processing element which are used in CGRA. Each components in processing element are simulated using Xilinx ISE. Finally, simulation results and final transient response of the schematic design of processing element are visualized. Keywords: Coarse-Grained Reconfigurable Architecture (CGRA), Reusable Context Pipelining, processing element. I. INTRODUCTIONNowadays, stream-based applications, such as multimedia, telecommunications, signal processing, and data encryptions, are the dominant workloads in many electronic systems. The real-time constraints of these applications, especially over portable devices, often have stringent energy and performance requirements. Many other military applications, including real-time synthetic aperture radar imaging, automatic target recognition, surveillance video processing, optical inspection, and cognitive radio systems, have similar needs. General purpose processors (GPPs), are widely used in conventional data-path oriented applications due to their flexibility and ease of use. However, they cannot meet the increasing requirements on performance, cost, and energy in the data streaming application domain due to their sequential software executions. The application-specific integrated circuits (ASICs) become inevitably a customized solution to meet these ever-increasing demands for highly repetitive parallel computations. It is reported that they are potentially two to three orders of magnitude more efficient than the processors in terms of combined performances of computational power, energy consumption, and cost. The long design cycle and high Non-Recursive Engineering (NRE) cost also become an obstacle to meet the stringent cost and time-to-market requirements. Reconfigurable architectures (RAs) have long been proposed as a way to achieve a balance between flexibility as of GPP and performance as of ASICs [1]. The hardware-based RA implementation is able to explore the spatial parallelism of the computing tasks in targeted applications, meanwhi...

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Section: Related Workmentioning

confidence: 99%

Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture

Murali¹

2018

IJRASET

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“…Reconfigurable architectures can be classified into finegrained, coarse-grained or hybrid grained on the basis of the granularity at which reconfiguration is done [10] . Coarse grained reconfigurable architectures (CGRAs), compared to FP-GAs, incur lower reconfiguration area (66% to 99.06%) and energy costs (88% to 98%) [11] , while FPGA is easier in partial reconfiguration since it utilizes the LUT (look-up table) as the basic operating unit, but the large amount of LUTs leads to huge configuration files and hence a long time for reconfiguration due to the overhead of bit-level reconfigurability [12] . CGRA-based multi-core architecture then emerged to accelerate the entire application by running separate kernels or inter-dependent kernels in parallel [13] , however, these architectures are not flexible enough to adaptively support various cases of the kernel-level parallelism (KLP) because the resources cannot be efficiently utilized under monotonous aggregation of multiple/many CGRAs, which results in either high power dissipation or performance bottleneck [14] .…”

Section: Introductionmentioning

confidence: 99%

HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array

Deng¹,

Lin²,

Zhu³

et al. 2020

J. Semicond.

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In order to accommodate the variety of algorithms with different performance in specific application and improve power efficiency, reconfigurable architecture has become an effective methodology in academia and industry. However, existing architectures suffer from performance bottleneck due to slow updating of contexts and inadequate flexibility. This paper presents an H-tree based reconfiguration mechanism (HRM) with Huffman-coding-like and mask addressing method in a homogeneous processing element (PE) array, which supports both programmable and data-driven modes. The proposed HRM can transfer reconfiguration instructions/contexts to a particular PE or associated PEs simultaneously in one clock cycle in unicast, multicast and broadcast mode, and shut down the unnecessary PE/PEs according to the current configuration. To verify the correctness and efficiency, we implement it in RTL synthesis and FPGA prototype. Compared to prior works, the experiment results show that the HRM has improved the work frequency by an average of 23.4%, increased the updating speed by 2×, and reduced the area by 36.9%; HRM can also power off the unnecessary PEs which reduced 51% of dynamic power dissipation in certain application configuration. Furthermore, in the data-driven mode, the system frequency can reach 214 MHz, which is 1.68× higher compared with the programmable mode.

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Design of reconfigurable array processor for multimedia application

Zhu

Lin

Wang

et al. 2017

Multimed Tools Appl

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Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture

Cited by 6 publications

References 18 publications

Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture

Design of Reusable Context Pipelining for Coarse Grained Reconfigurable Architecture

HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array

Design of reconfigurable array processor for multimedia application

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