2024
DOI: 10.1016/j.microrel.2024.115479
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Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

Sresta Valasa,
Venkata Ramakrishna Kotha,
Narendar Vadthiya
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