Introduction to Hardware/Software Codesign

Ha, Soonhoi; Teich, Jürgen; Haubelt, Christian; Glaß, Michael; Mitra, Tulika; Dömer, Rainer; Eles, Petru; Shrivastava, Aviral; Gerstlauer, Andreas; Bhattacharyya, Shuvra S.

doi:10.1007/978-94-017-7267-9_41

Cited by 7 publications

(2 citation statements)

References 26 publications

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“…The problem of mapping applications to many-core targets is often described by a specification graph [5,38,39] composed of (i) an application graph, (ii) an architecture graph, and (iii) a set of mapping edges that will be explained in the following.…”

Section: Fundamentalsmentioning

confidence: 99%

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

Letras,

Falk,

Teich

2024

IEEE Access

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Section: Fundamentalsmentioning

confidence: 99%

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

Letras,

Falk,

Teich

2024

IEEE Access

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“…They must also adapt to frequent workload changes due to the high mobility of connected devices in the network [1,2]. FPGAs are well-known platforms for handling services with high throughput demands, because of their high parallelization capability [3]. Furthermore, partial reconfiguration (PR), also known as dynamic function exchange (DFX), improves the system's flexibility.…”

Section: Introductionmentioning

confidence: 99%

A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications

Hosseinghorban

Kumar

2022

Electronics

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Rapid and continuous evolution in telecommunication standards and applications has increased the demand for a platform with high parallelization capability, high flexibility, and low power consumption. FPGAs are known platforms that can provide all these requirements. However, the evaluation of approaches, architectures, and scheduling policies in this era requires a suitable and open-source benchmark suite that runs on FPGA. This paper harnesses high-level synthesis tools to implement high-performance, resource-efficient, and easy-maintenance kernels for FPGAs. We provide various implementations of each kernel of PHY-Bench and WiBench, which are the most well-known benchmark suites for telecommunication applications on FPGAs. We analyze the execution time and power consumption of different kernels on ARM processors and FPGA. We have made all sources and documentation public for the benefit of the research community. The codes are flexible, and all kernels can easily be regenerated for different sizes. The results show that the FPGA can increase the speed by up to 19.4 times. Furthermore, we show that the power consumption of the FPGA can be reduced by up to 45% by partially reconfiguring a kernel that fits the size of the input data instead of using a large kernel that supports all inputs. We also show that partial reconfiguration can improve the execution time for processing a sub-frame in the uplink application by 33% compared to an FPGA-based approach without partial reconfiguration.

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HW/SW Co-Exploration and Co-Design

Mohamed

2024

Synthesis Lectures on Digital Circuits &Amp; Systems

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Introduction to Hardware/Software Codesign

Cited by 7 publications

References 26 publications

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications

HW/SW Co-Exploration and Co-Design

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