Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Jiang, Chunsheng; Xu, Jun

doi:10.1109/tnano.2016.2627808

Cited by 34 publications

(33 citation statements)

References 29 publications

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“…It should be remarked that the surface potential boosting of NC effect not only increases the tunneling probability but also improves the region over which the tunneling current is integrated. In addition to, considering Landau-Khalatnikov equation, high order terms of the ferroelectric charge cannot be neglected at high gate voltages that result in an enhanced negative capacitance effect [29]. The NC effect acts as the TFET performance booster near subthreshold (V g < V th ) and for the overdrive region (V g > V th ).…”

Section: Methodsmentioning

confidence: 99%

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

et al. 2018

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This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a trained-polycrystalline PZT capacitor and the tunnel FET (TFET) gate capacitance fabricated on a strained silicon-nanowire technology. We report a non-hysteretic switch configuration by combining a homojunction TFET and a negative capacitance effect booster, suitable for logic applications, for which the on-current is increased by a factor of 100, the transconductance by 2 orders of magnitude, and the low swing region is extended. The operation of a hysteretic negative capacitance TFET, when the matching condition for the negative capacitance is fulfilled only in a limited region of operation, is also reported and discussed. In this late case, a limited improvement in the device performance is observed. Overall, the paper demonstrates the main beneficial effects of negative capacitance on TFETs are the overdrive and transconductance amplification, which exactly address the most limiting performances of current TFETs.

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Section: Methodsmentioning

confidence: 99%

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

et al. 2018

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“…A non-hysteretic NC-GAA TFET is simulated and modeled by Jiang et al [5] with an assumption that the channel is fully depleted and mobile charges are absent in sub-threshold regime. H.Xu [6] modeled DG TFET with NC stack incorporating the effects of mobile charges for various ferro-electric materials with varying thickness.…”

Section: Introductionmentioning

confidence: 99%

“…So the simulation process of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) NC TFET requires LK equation along with TCAD. The MFIS structure can be replaced by Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) structure because of their closely matching properties [5]. Thus using TCAD, the Metal-Insulator-Semiconductor (MIS) structure is simulated and the effect of ferroelectric layer is realized using 1-D LK equation.…”

Section: Introductionmentioning

confidence: 99%

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

Shikha

James

Jacob³

et al. 2021

Preprint

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The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

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“…Underlapping and overlapping of the gate on drain can suppress the ambipolar conduction to a great extent [9][10]. Gate all around tunnel FET has better gate to channel control and hence it possesses better short channel performance than those with single or double gate structures [11][12]. Improvement in the sub-threshold slope and Ion/Ioff ratio of GAATFET device can be achieved by underlapping the drain junction [13].…”

Section: Introductionmentioning

confidence: 99%

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

Dutta

Soni

Pattanaik

2018

IJET

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This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average subthreshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

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Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Cited by 34 publications

References 29 publications

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

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