Investigation of various copper seed layers for copper electrodeposition applicable to ultralarge-scale integration interconnection

Abstract

As a superior substituent for the chemical-vapor deposition and physical-vapor deposition ͑PVD͒ Cu processes in an ultralarge-scale integrated interconnection, electrodeposition on two kinds of electroless-plated Cu seed layers was investigated. Co͑II͒ and formaldehyde were used as reducing agents for each electroless plating. Two samples of electroless-plated seed layers had relatively higher resistivity due to rough and irregular grains and weakly developed ͑111͒ texture, which are peculiarities of electroless plating. However, the Cu electrodeposited onto the electroless-plated seed showed reasonably good characteristics in resistivity, impurity level, crystalline structure, and surface roughness compared to those on the conventional PVD Cu seed. For the gap filling in the damascene structure, the electroless seed layer plating using formaldehyde and the subsequent electrodeposition on a patterned wafer showed an excellent filling profile without any voids or keyholes. After 400°C annealing in a N 2 atmosphere, adhesion between the Cu/barrier interfaces of electrodeposited copper on the two electroless-plated seeds was highly improved.

Orchestrated structure evolution: accelerating direct-write nanomanufacturing by combining top-down patterning with bottom-up growth

“…Direct-write tools (e.g. scanning beam and scanning probe systems) exhibit the flexibility of softwarereconfigurable instruments, but they are generally slow, which limits manufacturing throughput and increases production costs [5][6][7][8][9][10][11][12]. Soft lithography is an inexpensive method suitable for combining 'top-down' patterning with 'bottom-up' molecular self-assembly [5][6][7][11][12][13][14][15][16].…”

Atom Probe Tomography Characterization of Thin Copper Layers on Aluminum Deposited by Galvanic Displacement

“…Electroless deposition involves chemical instead of electrochemical reduction, and thus can be applied to substrates covered by electrically insulating oxide layers, enabling applications to base metals and interconnect diffusion barriers. 1,2 Galvanic displacement, a type of electroless deposition in which the substrate or an adsorbed species acts as the reducing agent, can produce nanometer-thickness films on semiconductors and noble metals. 3,4 Galvanic deposition of copper layers has been reported on oxide-covered materials such as aluminum, tantalum, as well as TiN and TaN diffusion barriers.…”

A Vapor-Phase Deposited Polymer Film to Improve the Adhesion of Electroless-Deposited Copper Layer onto Various Kinds of Substrates

“…Then the Cu deposited substrates were annealed at 120 °C for 3 h. The annealing process after the deposition of Cu is known to promote interlayer mixing at the interface between deposited Cu and the substrate and stabilize the interface. 32,33 Previous observation indicated that the promoted interlayer mixing by the annealing process induced the decrease in residual stress and thus caused an increase in the adhesion between the substrate and Cu film. 34 However, the annealing temperature was low enough to avoid the surface oxidation of Cu, as was confirmed by the X-ray diffraction patterns (see Figure S1 of the Supporting Information).…”