IP Address Lookup Algorithm Using a Vectored Bloom Filter

Abstract

-A Bloom filter is a space-efficient data structure popularly applied in many network algorithms. This paper proposes a vectored Bloom filter to provide a high-speed Internet protocol (IP) address lookup. While each hash index for a Bloom filter indicates one bit, which is used to identify the membership of the input, each index of the proposed vectored Bloom filter indicates a vector which is used to represent the membership and the output port for the input. Hence the proposed Bloom filter can complete the IP address lookup without accessing an off-chip hash table for most cases. Simulation results show that with a reasonable sized Bloom filter that can be stored using an on-chip memory, an IP address lookup can be performed with less than 0.0003 off-chip accesses on average in our proposed architecture.

A New Bloom Filter Architecture for FIB Lookup in Named Data Networking

“…Recently, numerous variants of the Bloom filter have been proposed [22][23][24][25] and applied to various network applications [26][27][28]. A functional Bloom filter [24,25] allocates multiple bits in a single cell, and hence it can return the value corresponding to an input as well as the membership information of that input by checking the stored value. In programming, for each element in a set, the return value corresponding to the element is stored in the k cells indicated by k hash indexes.…”

Vectored-Bloom Filter for IP Address Lookup: Algorithm and Hardware Architectures

“…The basic idea of the proposed vectored-Bloom filter (VBF) structure for IP address lookup was briefly introduced in References [31] and [32]. The VBF consists of m multi-bit vectors and each vector comprised of l bits contains an output port.…”

“…The proposed structure completes an IP address lookup by querying only the on-chip VBF without accessing the off-chip hash table. Depending on how output ports are programmed to the VBF, two different structures are possible [31]. The first structure involves making the l-bit vector represent up to 2 l − 2 output ports, zero and a conflict value, which is the value of 2 l − 1.…”

“…In this paper, we describe the second structure in detail including the hardware architecture which was not described in Reference [31]. Hence, Section 4 is completely a new section compared with Reference [31].…”

“…In this paper, we describe the second structure in detail including the hardware architecture which was not described in Reference [31]. Hence, Section 4 is completely a new section compared with Reference [31]. In Reference [32], even though the hardware architecture of the VBF implemented on the FPGA is briefly described, the proposed structure has not been evaluated through a behavior simulation and not been compared with other algorithms.…”