Is 3D integration the way to future dependable computing platforms?

Safiruddin, Saleh; Borodin, Demid; Lefter, Mihai; Voicu, George; Cotofana, Sorin

doi:10.1109/optim.2012.6231859

Cited by 6 publications

(1 citation statement)

References 31 publications

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“…3D Stacking Integrated Circuits (3D-SIC) technology, although originally proposed as an alternative to scaling in improving the performance of a circuit, also opens up new opportunities for reliable computing [5]. The idea behind the 3D-SIC approach is to partition the design in several smaller parts, and to implement each of them on a separate die.…”

Section: Introductionmentioning

confidence: 99%

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

Voicu

Cotofana

2013

2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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The reliability of near-future nano-meter range CMOS, and novel nano-computing devices is greatly affected by undesired effects of physical phenomena appearing due to continuous technology scaling. The emerging 3D-Stacking Integrated Circuits (3D-SIC) technology allows devices manufactured using different technologies, and thus with different reliability, to be stacked on top of each other and connected with low latency links. In this paper, we propose to take advantage of this new design space dimension, i.e., the individual reliability of devices, when using the von Neumann multiplexing redundancy technique. Our analysis suggests that multiplexing units reliability importance is determined by how high the error rate of individual gates in the system is, i.e., for high error rates the units at the end of the restoration chain are critical, while for low error rates the units at the beginning of the restoration chain are critical. We further introduce and evaluate the first, to the best of our knowledge, heterogeneous 3D-SIC multiplexing arrangements. Our results indicate that assuming that delay and area are doubled for a technology with an order of magnitude higher reliability, a heterogeneous multiplexing scheme with gates having high and medium error rates can achieve a reduction of 1.79× in delay and area, with a 9% loss in the Reliability Improvement Index (RII), over the homogeneous counterpart with only medium reliability gates. For medium and low error rates, a minimum 1% RII loss can be traded for a delay and footprint reduction of 5.66× and 4.25×, respectively.

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Section: Introductionmentioning

confidence: 99%