Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

Abstract

A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles

“…On the other hand, the computational cost of R(n) adds one squared modulus and one real moving average. The division in (5) is a costly operation [28] that can be avoided by multiplying ) (n R by the threshold with a cost of 1 real product. The hardware cost of this coarse time synchronization algorithm is: 5 real multipliers, 14 real adders, 160 delay lines and a comparison circuit (combinational logic).…”