Kendall Square multiprocessor: Early experiences and performance

Dunigan, T.H.

doi:10.2172/10142365

Cited by 30 publications

(15 citation statements)

References 19 publications

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“…Completeness and hierarchical organization are crucial, because not all of the performance factors can be measured directly, and must be inferred from others. LCA also required completeness, however, the authors were fortunate enough to work with a platform [15] that allowed for direct measurement of all hardware delays, which cannot be done on current hardware.…”

Section: Resultsmentioning

confidence: 99%

Deconstructing the overhead in parallel applications

Roth

Best²,

Mustard

et al. 2012

2012 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-Performance problems in parallel programs manifest as lack of scalability. These scalability issues are often very difficult to debug. They can stem from synchronization overhead, poor thread scheduling decisions, or contention for hardware resources, such as shared caches. Traditional profiling tools attribute program cycles to different functions, but do not generate immediate insight into issues limiting scalability. Profiling information is very program-specific and is usually processed manually by a human expert in a time-consuming and cumbersome process.Our experience in tuning performance of parallel applications led us to discover that performance tuning can be considerably simplified, and even to some degree automated, if profiling measurements are organized according to several intuitive performance factors common to most parallel programs. In this work we present these factors and propose a hierarchical framework composing them. We present three case studies where analyzing profiling data according to the proposed principle led us to improve performance of three parallel programs by a factor of 6-20×. Our work lays foundation for new ways of organizing and visualizing profiling data in performance tuning tools.

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Section: Resultsmentioning

confidence: 99%

Deconstructing the overhead in parallel applications

Roth

Best²,

Mustard

et al. 2012

2012 IEEE International Symposium on Workload Characterization (IISWC)

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“…SCI was designed for off-chip interconnect, where tradeoffs in power and performance are very different than in on-chip interconnects. The KSR (Kendall Square Research) machine [13] uses a hierarchical ring design that resembles HiRD, yet these techniques are not disclosed in detail and, to our knowledge, have not been publicly evaluated in terms of energy efficiency. Other Ring-based Topologies: Spidergon [7] proposes a bidirectional ring augmented with links that directly connect nodes opposite each other on the ring.…”

Section: E Comparison Against Other Ring Configurationsmentioning

confidence: 99%

Design and Evaluation of Hierarchical Rings with Deflection Routing

Ausavarungnirun

Fallin

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice some of the key benefits of rings by reintroducing more complex in-ring buffering and buffered flow control. Our goal in this paper is to design a new hierarchical ring interconnect that can maintain most of the simplicity of traditional ring designs (i.e., no in-ring buffering or buffered flow control) while achieving high scalability as more complex buffered hierarchical ring designs.To this end, we revisit the concept of a hierarchical-ring networkon-chip. Our design, called HiRD (Hierarchical Rings with Deflection), includes critical features that enable us to mostly maintain the simplicity of traditional simple ring topologies while providing higher energy efficiency and scalability. First, HiRD does not have any buffering or buffered flow control within individual rings, and requires only a small amount of buffering between the ring hierarchy levels. When inter-ring buffers are full, our design simply deflects flits so that they circle the ring and try again, which eliminates the need for in-ring buffering. Second, we introduce two simple mechanisms that together provide an end-to-end delivery guarantee within the entire network (despite any deflections that occur) without impacting the critical path or latency of the vast majority of network traffic.Our experimental evaluations on a wide variety of multiprogrammed and multithreaded workloads and synthetic traffic patterns show that HiRD attains equal or better performance at better energy efficiency than multiple versions of both a previous hierarchical ring design and a traditional single ring design. We also extensively analyze our design's characteristics and injection and delivery guarantees. We conclude that HiRD can be a compelling design point that allows higher energy efficiency and scalability while retaining the simplicity and appeal of conventional ring-based designs.

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“…A single processor generates a maximum of 40 MBs against the ring. LINPACK 100 x 100 double-precision on a single processor was 15 Mflops [3].…”

Section: Kendall Squarementioning

confidence: 99%