Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy

Krygowski, C. A.; Almog, Eli; Bair, D. G.; Breil, R.; Dittmann, Gero; Gott, R.M.; Shah, A. D.; Thompto, Brian W.

doi:10.1147/jrd.2011.2178737

Cited by 3 publications

(2 citation statements)

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“…A hybrid RAIM (redundant array of independent memory) method was used for the IBM zEnterprise processor verification which contained 80 configurable cores. This verification environment was based on combination of formal verification and random verification, developing configurable stimulus to improve function coverage [19].…”

Section: Related Workmentioning

confidence: 99%

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Pan¹,

Tang²,

Guodong³

et al. 2014

TOCSJ

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Abstract:Functional verification has become a major challenge in the chip design area. To improve the efficiency of verification, it is necessary to choose appropriate verification method and tools. An important aspect of functional verification is RTL verification, simulation-based verification is main method in RTL verification. Based on FT-8 multicore processor, we developed a configurable test stimulus acceleration method, loading the test stimulus into memory and L2 cache to speed up the processor instructions fetch, which can shorten simulation cycle and simulation time, reduce the verification cost and guaranteed the correctness of design.

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Section: Related Workmentioning

confidence: 99%

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Pan¹,

Tang²,

Guodong³

et al. 2014

TOCSJ

View full text Add to dashboard Cite

show abstract

“…Coverage-Driven Verification: The term "functional coverage" is used to describe a parameter that quantifies the functional space that has been covered, as opposed to code coverage that quantifies how much of the implemented design has been covered by a given test suites [46,95]. Directed simulation can then be used to cover corner test space at the end of the verification cycle.…”

Section: Verification Methodsmentioning

confidence: 99%

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Yang¹

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Design and verification of DEFLATE acceleration as an architected instruction in z15

Klein¹,

Misra²,

Abali³

et al. 2020

IBM J. Res. & Dev.

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Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy

Cited by 3 publications

References 10 publications

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Design and verification of DEFLATE acceleration as an architected instruction in z15

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