Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors

Cai, Linlin; Chen, Wangyong; Du, Gang; Zhang, Xing; Liu, Xiaoyan

doi:10.1109/ted.2018.2825498

Cited by 87 publications

(34 citation statements)

References 26 publications

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“…Despite this, the NW FET still delivers the highest I ON /I OFF ratio. These NW FET characteristics, together with the possibility of stacking them vertically [3], [6], [7], suggest that the NW architecture makes an excellent candidate for low power applications. The NS FET has an I ON /I OFF ratio 37% smaller than the ratio of the NW FET and delivers a slightly better performance in the sub-threshold than that of the FinFET.…”

Section: Benchmarksmentioning

confidence: 99%

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early I ON saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

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Section: Benchmarksmentioning

confidence: 99%

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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“…In advanced CMOS technology, there are other key reliability issues concerned, such as self-heating (SH) and random telegraph noise (RTN), which are induced by small scale of 3D device [ 300 , 301 , 302 , 303 , 304 , 305 , 306 , 307 , 308 ].…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

“…Usually, self-heating (SH) is very sensitive to HCI and BTI [ 300 , 301 , 302 ], and self-heating of nanosheets could induce variability of devices, which makes the reliability of nanosheets more complicated, as shown in Figure 43 [ 303 ]. Furthermore, nanosheets show better resilience to a SH than FinFETs, and the SH of nanosheets is very sensitive to the structure of nanosheets, such as the width of nanosheets [ 304 ].…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…In CMOS miniaturization, the random telegraph noise (RTN) needs to be paid more attention to as an indicator for problem source acting on the transistor performance. For advanced CMOS, the self-heating becomes a more serious matter and this has been widely studied [176,177,178,179]. It has been reported that PFET has higher RTN than NFET due to an extrinsic origin caused by SiGe in the S/D [177].…”

Section: Reliabilitymentioning

confidence: 99%

“…Moreover, based on simulation results, the nano-sheet devices exhibit better resilience to a self-heating effect (SHE) in comparison to the FinFETs [177]. In general, SHE is very sensitive to layout design, hot-carrier degradation (HCD), and bias temperature instability (BTI) [178,179]. In the layout design of the nano sheet devices, the width of the nano sheet (Wsh) is the key parameter, which provides a flexible choice to make trade-offs between thermal properties and electrical performance in nanosheet FETs, compared with the NW FETs (see Figure 28) [179].…”

Section: Reliabilitymentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors

Cited by 87 publications

References 26 publications

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

State of the Art and Future Perspectives in Advanced CMOS Technology

Miniaturization of CMOS

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