Leak Resistant Arithmetic

Bajard, Jean-Claude; Imbert, Laurent; Liardet, Pierre-Yvan; Téglia, Yannick

doi:10.1007/978-3-540-28632-5_5

Cited by 57 publications

(76 citation statements)

References 26 publications

(42 reference statements)

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“…According to the leak resistant arithmetic (LRA) concepts [9], the RNS moduli can be randomized before each exponentiation. This countermeasure acts as a message blinding technique because and offers a high degree of randomization to the data.…”

Section: The Randomized Exponentiation and The Device Under Testmentioning

confidence: 99%

“…Apart from these well known tricks, randomization can also take place at the arithmetic level. The LRA concept [9], based on the Residue Number System, seems to be a robust, yet efficient [24,25] alternative to more expensive (hardware) countermeasures.…”

Section: Introductionmentioning

confidence: 99%

“…Our attack is unsupervised because it does not require any a priori knowledge of the device, in particular we did not use the public key or send any chosen messages in order to learn the characteristics of the device. The chip under attack is a constant-time, RNS-based FPGA implementation of RSA protected with the Leak Resistant Arithmetic [9] and exponent blinding. Since all manipulated data is randomized, we explore the remaining leakages due to control instructions and memory activities.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Attacking Randomized Exponentiations Using Unsupervised Learning

Perin

Imbert

Torres

et al. 2014

Constructive Side-Channel Analysis and Secure Design

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Abstract. Countermeasures to defeat most of side-channel attacks on exponentiations are based on randomization of processed data. The exponent and the message blinding are particular techniques to thwart simple, collisions, differential and correlation analyses. Attacks based on a single (trace) execution of exponentiations, like horizontal correlation analysis and profiled template attacks, have shown to be efficient against most of popular countermeasures. In this paper we show how an unsupervised learning can explore the remaining leakages caused by conditional control tests and memory addressing in a RNS-based implementation of the RSA. The device under attack is protected with the exponent blinding and the leak resistant arithmetic. The developed attack combines the leakage of several samples over the segments of the exponentiation in order to recover the entire exponent. We demonstrate how to find the points of interest using trace pre-processing and clustering algorithms. This attack can recover the exponent using a single trace.

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Section: The Randomized Exponentiation and The Device Under Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Attacking Randomized Exponentiations Using Unsupervised Learning

Perin

Imbert

Torres

et al. 2014

Constructive Side-Channel Analysis and Secure Design

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“…We provide formula for this kind of randomization along with the required updates of the constants involved in RNS computations. The complexity analysis shows that this approach can be advantageous for a lower level of randomization compared to [1]. In other words this provides a trade-off between efficiency and randomization.…”

mentioning

confidence: 99%

Trade-Off Approaches for Leak Resistant Modular Arithmetic in RNS

Nègre

Perin²

2015

Information Security and Privacy

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On an embedded device, an implementation of cryptographic operation, like an RSA modular exponentiation [12], can be attacked by side channel analysis. In particular, recent improvements on horizontal power analysis [3,10] render ineffective the usual counter-measures which randomize the data at the very beginning of the computations [4,2]. To counteract horizontal analysis it is necessary to randomize the computations all along the exponentiation. The leak resistant arithmetic (LRA) proposed in [1] implements modular arithmetic in residue number system (RNS) and randomizes the computations by randomly changing the RNS bases. We propose in this paper a variant of the LRA in RNS: we propose to change only one or a few moduli of the RNS basis. This reduces the cost of the randomization and makes it possible to be executed at each loop of a modular exponentiation.Keywords: Leak resistant arithmetic, randomization, modular multiplication, residue number system, RSA. IntroductionNowadays, the RSA cryptosystem [12] is constantly used in e-commerce and credit card transactions. The main operation in RSA protocols is an exponentiation x K mod N where N is a product of two primes N = pq. The secret data are the two prime factors of N and the private exponent K used to decrypt or sign a message. The actual recommended size for N is around 2000-4000 bits to insure the intractability of the factorization of N . The basic approach to perform efficiently the modular exponentiation is the square-and-multiply algorithm: it scans the bits k i of the exponent K and performs a sequence of squarings followed by a multiplication only when k i is equal to one. Thus the cryptographic operations are quite costly since they involve a few thousands of multiplications or squarings modulo a large integer N .A cryptographic computation performed on an embedded device can be threaten by side channel analysis. These attacks monitor power consumption or electromagnetic emanation leaked by the device to extract the secret data. The simplest attack is the simple power analysis (SPA) [8] which applies when the power trace of a modular squaring and a modular multiplication are different. This makes it possible to read the sequence of operations on the power trace of an exponentiation and then derive the key bits of the exponent. This attack is easily overcome by using an exponentiation algorithm like the Montgomeryladder [6] which render the sequence of operation uncorrelated to the key bits. A more powerful attack, the differential power analysis (DPA) [8], makes this counter-measure against SPA inefficient. Specifically, DPA uses a large number of traces and correlate the intermediate values with the power trace: it then track the intermediate value all along the computation and then guess the bits of the exponent. Coron in [4] has shown that the exponentiation can be protected from DPA by randomizing the exponent and by blinding the integer x. Recently the horizontal attacks presented in [13,3] require only one power trace of an expone...

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“…Successful fault injection on FPGAs is reported by Maingot et al in [16]. The concept of spatial jitter for hardware implementations has been addressed in [2] and [8], where architectures are proposed that consist of several identical elementary cells. An algorithm's suboperations are randomly mapped on these cells.…”

Section: Introductionmentioning

confidence: 99%

Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration

Mentens

Gierlichs

Verbauwhede

Cryptographic Hardware and Embedded Systems – CHES 2008

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Abstract. Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead needed to provide reconfigurability. We show that dynamic reconfiguration can also improve the resistance of cryptographic systems against physical attacks. First, we demonstrate how dynamic reconfiguration can realize a range of countermeasures which are standard for software implementations and that were practically not portable to hardware so far. Second, we introduce a new class of countermeasure that, to the best of our knowledge, has not been considered so far. This type of countermeasure provides increased resistance, in particular against fault attacks, by randomly changing the physical location of functional blocks on the chip area at run-time. Third, we show how fault detection can be provided on certain devices with negligible area-overhead. The partial bitstreams can be read back from the reconfigurable areas and compared to a reference version at run-time and inside the device. For each countermeasure, we propose a prototype architecture and evaluate the cost and security level it provides. All proposed countermeasures do not change the device's input-output behavior, thus they are transparent to upper-level protocols. Moreover, they can be implemented jointly and complemented by other countermeasures on algorithm-, circuit-, and gate-level.

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Leak Resistant Arithmetic

Cited by 57 publications

References 26 publications

Attacking Randomized Exponentiations Using Unsupervised Learning

Attacking Randomized Exponentiations Using Unsupervised Learning

Trade-Off Approaches for Leak Resistant Modular Arithmetic in RNS

Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration

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