Learning-based BTI stress estimation and mitigation in multi-core processor systems

Abbas, Hayder M.; Halak, Basel; Zwoliński, Mark

doi:10.1016/j.micpro.2020.103713

Cited by 3 publications

(3 citation statements)

References 19 publications

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“…After computation criticality of each gate, gates are ranked in descending order based on the computed criticality described in Eq. (18). Then, the most critical gate is picked out for assigning high Vth.…”

Section: ) Optimization Approach #1:greedy-based Methods (Gero)mentioning

confidence: 99%

“…However, considering the interdependencies between BTI and PV [13], [14], such separate analysis leads to inaccurate and unrealistic results. Recently, some papers have addressed the combined impacts of process variability and NBTI or BTI at different levels of abstraction such as device-level [9], gatelevel [15]- [17], and architecture-level [18]- [20]. Siddiqua et al,in [21] explored both NBTI and PV in an SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

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Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

et al. 2021

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In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation-and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dualthreshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

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Section: ) Optimization Approach #1:greedy-based Methods (Gero)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

et al. 2021

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“…A unified physical and statistical compact model of BTI on the down-scaling technology nodes was developed, which realized cycle-to-cycle/device-to-device reliability evaluations [57]. In [58], data from workloads through machine learning techniques were extracted to establish the aging model. But these studies are fairly preliminary at the moment.…”

Section: Model Formulamentioning

confidence: 99%

Development and Challenges of Reliability Modeling From Transistors to Circuits

Yang

Sang

Wang

et al. 2023

IEEE J. Electron Devices Soc.

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The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.

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Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level

Ranjbar

Klemme

Genßler

et al. 2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Learning-based BTI stress estimation and mitigation in multi-core processor systems

Cited by 3 publications

References 19 publications

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Development and Challenges of Reliability Modeling From Transistors to Circuits

Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level

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