LFSR-based test-data compression with self-stoppable seeds

Koutsoupia,; Kalligeros,; Kavousianos,; Nikolos,

doi:10.1109/date.2009.5090897

Cited by 7 publications

(8 citation statements)

References 22 publications

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“…of degree D P and p 0 = 1 10: for h = 1 to |H| do 11: F h (x) ← generate pol. of degree D F h 12: end for 13: H (lines 3 to 7). In line 5 the maximum degree for each polynomial F h (x) is computed.…”

Section: A Computing All Polynomials Of a Given Degreementioning

confidence: 99%

“…Several works use/assume this proposition for the selection of their characteristic polynomial. Some of these works are seed compression [15], on-line seed loading [14], [12], multiple polynomial LFSR structures [6], [10], multiple seeds to generate one or more tests [13], LFSR reseeding with additional hardware to control the LFSR behavior [8], [18], [2], [19], and reseeding targeting additional features like defect-oriented reseeding [9], [24], unmodeled faults reseeding [26] and low-power dissipation [17], [16]. What is common in all these methodologies is that the polynomial used to implement the LFSR is fixed a priori in an arbitrary manner.…”

Section: Introductionmentioning

confidence: 99%

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On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Acevedo

Kagaris

2016

IEEE Trans. Comput.

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In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax + 20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the BerlekampMassey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the "trialand-error" Smax + 20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage.

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Section: A Computing All Polynomials Of a Given Degreementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Acevedo

Kagaris

2016

IEEE Trans. Comput.

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“…In the proposed scheme, in order to reduce the memory requirements without sacrificing the fully exploitation of the encoding capability of the LFSR, we use the encoding method described in [10]. According to [10], a unique vector called "stop slice" with the minimum possible number of defined bits is embedded to the end of each encoded sequence.…”

Section: Test Data Encoding Selection For In-field Testingmentioning

confidence: 99%

“…In Section 2, we show the suitability of the LFSR-based Test-Data Compression with Self-Stoppable Seeds method [10] for in-field testing. In Section 3, the proposed method is presented for hard and soft real-time systems.…”

Section: Introductionmentioning

confidence: 99%

Preemptive built-in self-test for in-field structural testing

Sismanoglou

Pitsios

Nikolos

2015

Sixteenth International Symposium on Quality Electronic Design

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One-time factory testing of VLSI components after fabrication is insufficient in the deep submicron era. The products must be tested periodically in the field of application. Due to the complexity of the Systems on a Chip (SoCs), huge amounts of test data are required. However in many embedded systems the capacity of the available memory is a limited resource. Besides in real time embedded systems the in-field testing activities should be accommodated with the real-time constraints of the system. In this paper we at first show the suitability of the LFSR-based Test-Data Compression with Self-Stoppable Seeds method [10] for in-field testing and we give the required enhancements so that can be used as a Preemptive Built-In Self-Test mechanism for in-field testing that is applied at the idle time intervals of a hard real-time embedded system with sporadic tasks. Then, based on a probabilistic model and extensive simulations, we show that in the proposed method the time required to apply all the test vectors to the Circuit Under Test is many times smaller than the time required when the testing procedure consists from one or more non-preemptive test sessions. The proposed method achieves lower energy consumption for testing and significantly smaller fault detection latency times.

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“…This also has the disadvantage of employing expensive communication infrastructure for the test data which can negatively affect the performance of the system. Many works have been done for improving LFSR based BIST architectures [12][13][14], LFSR reconfiguration [15], and optimized reseeding [16][17][18] to get high fault coverage and less test application time. In order to achieve high fault coverage alongside with low test application time, some works [8][9][10][11] have attempted to use hybrid BIST methods that include scan based approaches.…”

Section: Introductionmentioning

confidence: 99%

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

Sadredini

Najafi

Navabi

2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

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Abstract-By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents a multistage test strategy to be implemented on a BIST architecture for reducing test time of a simple core as solution for more global application of SoC testing strategy. This strategy implements its test pattern generation and output response analyzer in a BILBO architecture. The proposed method benefits from an irregular polynomial BILBO (IP-BILBO) structure to improve its test results. Experimental results on ISCAS-89 benchmark circuits show an average of 35% improvement in test time in proportion to pervious work.

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LFSR-based test-data compression with self-stoppable seeds

Cited by 7 publications

References 22 publications

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Preemptive built-in self-test for in-field structural testing

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

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