LHCb Upgrade: from 1 to 40 MHz

Abstract

The fully upgraded detector will use a new front-end electronics to readout collision events at 40MHz. A new fully software based trigger will be implemented and will increase the trigger efficiencies, specially in the hadronic decay channels. The silicon vertex detector baseline design will use pixel technology. The upgraded detector will accumulate in excess of 50fb −1 of data, giving radiation doses of 4 × 10 15 n eq and above at the edge of the silicon. This requires an efficient cooling system to avoid thermal runaway. The existing cooling system based on evaporative CO 2 will be adapted. A strong R&D program has started on sensor material and radiation hardness, thickness, guard ring structures and the final module layout. In parallel the design of a new radiation hard ASIC for pixel readout, namely VELOpix, is progressing well. The main challenge will be the large multi Gbps data rates on and off this chip. In terms of precision, pattern recognition and impact parameter resolution, the goal is to achieve the same or better performance than the current vertex detector at the LHCb experiment.