Linear Model-Based Testing of ADC Nonlinearities

Wegener, Carsten; Kennedy, Michael Peter

doi:10.1109/tcsi.2003.821281

Cited by 25 publications

(5 citation statements)

References 11 publications

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“…Since the above methods are based on the histogram test method, they generally require a large volume of code measurements along with high precision input (ramp/sinusoidal) signals. Linearity tests using a linear modeling technique are discussed in [8]- [10]. In this paper, test time is reduced by measuring only a defined subset of code transition levels, which is significantly smaller than the required number of code measurements for histogram-based test.…”

Section: Prior Workmentioning

confidence: 99%

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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A low-cost linearity test methodology for high-resolution analog-to-digital converters (ADCs) is presented in this paper. Linearity testing of ADCs requires high-precision digital-to-analog conversion (DAC) capability, commonly 3-bit higher resolution than the ADC under test. Further, a large number of ADC output data samples must be collected making conventional histogram testing impractical for high-resolution ADCs with 18-24 bit precision. In the proposed test methodology, two low-precision and low-cost DACs are used to generate a high-resolution ADC test stimulus. Significant reductions in test cost and test time are achieved by using low-cost instrumentation and by making fewer measurements than required for conventional histogram test. A least-squares-based polynomial fitting approach is used to determine the transfer function of the ADC under test. The generated transfer function is used to compute the non-linearity of the ADC accurately. No assumption is made regarding the linearity of the lower precision signal generators (DACs) used in the testing procedure. Software simulations and hardware experiments are performed to validate the proposed test methodology.Index Terms-Analog-to-digital converters (ADCs), automated test equipment (ATE), built-in-self-test (BIST), device under test (DUT), differential nonlinearity, digital-to-analog converters (DACs), integral nonlinearity.

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Section: Prior Workmentioning

confidence: 99%

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Kook

Choi

Chatterjee

2013

IEEE Trans. VLSI Syst.

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“…Another category of new methods is the one we can call model-based [13][14][15][16][17][18]. Among them, there are techniques relying on the development of a linear model using a reduced set of variables [13,14].…”

Section: B Reducing Test Timementioning

confidence: 99%

“…Among them, there are techniques relying on the development of a linear model using a reduced set of variables [13,14]. Strictly speaking, this does not relax the tester requirements but the number of specifications to be measured.…”

Section: B Reducing Test Timementioning

confidence: 99%

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems

Barragán

Huertas

Rueda

et al. 2010

2010 Fifth IEEE International Symposium on Electronic Design, Test &Amp; Applications

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“…However, deducing the static performances from a spectral test can only be applied in some cases and cannot be generalized. Model-based ADC linearity test techniques are proposed in [20], [21].…”

Section: Introductionmentioning

confidence: 99%

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

Laraba

Stratigopoulos

Mir

et al. 2015

IEEE Trans. Circuits Syst. I

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International audienceTesting the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases the efficiency and accuracy of the method. We show that by exploiting some inherent properties in the architecture of pipeline ADCs we can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test. The proposed method is demonstrated on a 55 nm 11-bit 2.5-bits/stage pipeline ADC

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Linear Model-Based Testing of ADC Nonlinearities

Cited by 25 publications

References 11 publications

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

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