Local variations compensation with DLL-based Body Bias Generator for UTBB FD-SOI technology

Mauricio, Joan; Moll, Francesc

doi:10.1109/newcas.2015.7182005

Cited by 10 publications

(3 citation statements)

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“…Notice that the full text of the publications carried out during this thesis is annexed at the end of the document with the aim of making this thesis dissertation easier to follow. The first article was presented in System-on-Chip Conference (SoCC) [56], the second was published in IEEE Transactions on Electron Devices (TED) journal [57] and the final article was presented in New Circuits And Systems Conference (NEWCAS) [58].…”

Section: Document Structurementioning

confidence: 99%

“…Additionally, there is a SLEEP flag that forces the maximum RBB during idle periods. This circuit is described more in detail in Appendix C [58]. The charge pump design of the FBB+RBB also increases its complexity in comparison with the first proposal.…”

Section: Fbb+rbb Generator Circuit Proposalmentioning

confidence: 99%

“…Otherwise, FBB is produced by discharging C3 and C4 capacitors with DCHG signal. Further implementation details can be found in Appendix C [58].…”

Section: Fbb+rbb Generator Circuit Proposalmentioning

confidence: 99%

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Monitor amb control strategies to reduce the impact of process variations in digital circuits

Mauricio Ferré

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As CMOS technology scales down, Process, Voltage, Temperature and Ageing (PVTA) variations have an increasing impact on the performance and power consumption of electronic devices. These issues may hold back the continuous improvement of these devices in the near future. There are several ways to face the variability problem: to increase the operating margins of maximum clock frequency, the implementation of lithographic friendly layout styles, and the last one and the focus of this thesis, to adapt the circuit to its actual manufacturing and environment conditions by tuning some of the adjustable parameters once the circuit has been manufactured. The main challenge of this thesis is to develop a low-area variability compensation mechanism to automatically mitigate PVTA variations in run-time, i.e. while integrated circuit is running. This implies the development of a sensor to obtain the most accurate picture of variability, and the implementation of a control block to knob some of the electrical parameters of the circuit. A mesura que la tecnologia CMOS escala, les variacions de Procés, Voltatge, Temperatura i Envelliment (PVTA) tenen un impacte creixent en el rendiment i el consum de potència dels dispositius electrònics. Aquesta problemàtica podria arribar a frenar la millora contínua d'aquests dispositius en un futur proper. Hi ha diverses maneres d'afrontar el problema de la variabilitat: relaxar el marge de la freqüència màxima d'operació, implementar dissenys físics de xips més fàcils de litografiar, i per últim i com a tema principal d'aquesta tesi, adaptar el xip a les condicions de fabricació i d'entorn mitjançant la modificació d'algun dels seus paràmetres ajustables una vegada el circuit ja ha estat fabricat. El principal repte d'aquesta tesi és desenvolupar un mecanisme de compensació de variabilitat per tal de mitigar les variacions PVTA de manera automàtica en temps d'execució, és a dir, mentre el xip està funcionant. Això implica el desenvolupament d'un sensor capaç de mesurar la variabilitat de la manera més acurada possible, i la implementació d'un bloc de control que permeti l'ajust d'alguns dels paràmetres elèctrics dels circuits.

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Section: Document Structurementioning

confidence: 99%

Section: Fbb+rbb Generator Circuit Proposalmentioning

confidence: 99%