Locality-aware data replication in the Last-Level Cache

Kurian, George Thomas; Devadas, Srinivas; Khan, Omer

doi:10.1109/hpca.2014.6835921

Cited by 31 publications

(34 citation statements)

References 34 publications

(31 reference statements)

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“…We exploit heterogeneous interconnects and optimize caching strategy targeting on shared written blocks with high coherence overhead. Some works [11,15] exploit block placement and/or replication policy in LLC based on block access patterns, which optimize block placement on LLC. While our work carefully orchestrates caching strategy for different blocks in the memory hierarchy.…”

Section: Related Workmentioning

confidence: 99%

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence

Liu

Huang

et al. 2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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Emerging heterogeneous interconnects have shown lower latency and higher throughput, which can improve the efficiency of communication and create new opportunities for memory system designs. In this paper, transmission lines are employed as a latency-optimized network and combined with a packet-switched network to create heterogeneous interconnects improving the efficiencies of on-chip communication and cache coherence. We take advantage of this heterogeneous interconnect design, and keep cache coherence adaptively based on data locality. Different type of messages are adaptively directed through selected medium of the heterogeneous interconnects to enhance cache coherence effectiveness. Compared with a state-of-the-art coherence mechanism, the proposed technique can reduce the coherence overhead by 24%, reduce the network energy consumption by 35%, and improve the system performance by 25% on a 64-core system.

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Section: Related Workmentioning

confidence: 99%

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence

Liu

Huang

et al. 2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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“…omparative Analysis of L3 Cache Optimizing Techniques ome the issue, many researchers have proposed replication techniques. Kurian et al [39] have sive-Shared-Invalid) protocol, if one private cache L1 of core A holds data and another private cache of other core B requests for the same data, then it sends request on network [10]. If requested data in private cache of Core A are valid and the respective core is free to respond back, then Core B is given the requested data and data block is marked with Shared state; otherwise core B needs to wait.…”

Section: Data Replication On Last Level Cachementioning

confidence: 99%

“…Applications used multithreading on multicores to get faster operations. In order to improve performance and energy efficiency good scalability for multicore and assurance of single core performance is important [39].…”

Section: Introductionmentioning

confidence: 99%

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On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Zahid

Khurshid

Memon

2018

ITC

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With the increasing need of computational power the trend towards multicore processors is ubiquitous. The current on-chip architecture comprises multiple cores which usually share last level cache which can be physically distributed on chip. In order to provide system predictability, especially for a real time system where quality of service (QoS) depends on minimum miss rates and low worst case execution time (WCET) for applications running on different cores, efficient cache management techniques are required. Since memory hierarchy and its management is the key of overall system performance and access to off-chip memory for data consumes many clock cycles along with many units of power it is important to restrict the off-chip access and provide the optimum solution for the on-chip access. To increase performance and energy efficiency, various techniques are proposed. This article aims to provide the researchers with the state-of-the-art critical review of the various approaches that focus on data replication and cache partitioning techniques for L3 cache. The existing literature is presented through several classifications based on appropriate design and algorithm. Maintaining energy efficient system is a crucial challenge for multicore processors. We have discussed various techniques which address upscaling performance without compromising on energy efficiency. Lastly, different literature work is discussed where authors evaluate cache and/or various processors for high performance applications such as bioinformatics, image and video processing, IOT applications and applications using DSP processors.

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“…T HE increasing bandwidth demand of current memory-intensive applications incurs significant data movement that negatively impacts off-chip bandwidth, on-chip memory access latency, and energy consumption [1] [2] [3] [4]. To reduce data transfer between on-chip and off-chip memory components, commercial multi-core systems utilize multi-level cache methodology [5] [6] [7] whereby fast, low-capacity, and high leakage power SRAM arrays are employed in the upperlevels of cache, i.e.…”

Section: Introductionmentioning

confidence: 99%

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

Khoshavi

DeMara

2018

IEEE Access

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As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this work concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique partitions L2 cache into two STT-RAM arrangements with different write performance and data retention time. The retentionrelaxed STT-RAM arrays are utilized to effectively deal with the regular L2 cache requests while the high retention STT-RAM arrays in L2 are selected for maintaining repeatedly read accessed cache blocks from LLC by incurring negligible energy consumption for data retention. Our experimental results show that the proposed technique can reduce the mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average across PARSEC benchmark suite while significantly decreasing the total L2 energy consumption compared to conventional SRAMbased L2 design.

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Locality-aware data replication in the Last-Level Cache

Cited by 31 publications

References 34 publications

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization

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