Locating Open-Channels in Octagon Networks on Chip-Microprocessors

Bhowmik, Biswajit; Biswas, Santosh; Deka, Jatindra Kumar; Bhattacharya, Bhargab B.

doi:10.1109/isvlsi49217.2020.00044

Cited by 8 publications

(1 citation statement)

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“…The NoC is organized and structured by its topology [11], which includes the whole arrangement of routers and cores, as well as the ways used to comprehend routing, arbitration, buffering, flow management, and switching techniques [12]. The data flow control refers to the amount of data traffic or intensity that passes through the routers and channels.…”

Section: Related Workmentioning

confidence: 99%

Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

Jain¹,

Dwivedi²,

Alshazly³

et al. 2022

Computers, Materials &Amp; Continua

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The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with 'N' bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

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Section: Related Workmentioning

confidence: 99%