Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene

Abstract

An overview of future logic scaling options both for devices and interconnects will be provided from technology point of view, including Front-End-Of-Line (FEOL), Middle-Of-Line (MOL) and Back-End-Of-Line (BEOL) modules [1][2][3][4]. The aim is to provide a perspective for the coming 10years in terms of CMOS scaling scenarios. To enable more efficient computing, both device and interconnect architectures are expected to change. The device trend from today's conventional FinFet to Nanosheet then Forksheet then to CFET and eventually to 2D materials will be explained [3,5,6]. This is alongside with the wide deployment of EUV lithography into BEOL, MOL, FEOL paving a cost-effective patterning. Track height scaling along with the use of scaling boosters is the natural path to follow. It is accompanied by significant changes in MOL and BEOL modules as well. One example is the potential inflection point from classical dual damascene modules towards metal patterning based self-aligned semi damascene. This in combination with airgaps can provide an attractive RC tradeoff. Another example is backside power delivery enabled by the use of nano-TSVs [7,8]. During the talk several more examples will be shown.