Low complexity and hardware-friendly spectral modular multiplication

Chen, Donald Donglong; Yao, Gavin Xiaoxu; Koç, Çetin Kaya; Cheung, Ray C. C.

doi:10.1109/fpt.2012.6412162

Cited by 4 publications

(4 citation statements)

References 25 publications

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“…It is crucial to perform modular multiplication in GF (2 13 − 1) efficiently, since it directly influences the efficiency of multiplication in GF ((2 13 − 1) 13 ). There is a 16-bit hardware multiplier available on most MSP430 microcontrollers.…”

Section: Modular Multiplicationmentioning

confidence: 99%

“…In [28], an algorithm was proposed for performing repeated modular multiplications in the frequency domain for application to RSA. Hardware architectures for modular multiplication in the frequency domain, for RSA bitlengths, were proposed in [13] and [34], with actual implementation results. Finally in [14], a frequency domain hash function was proposed.…”

Section: Introductionmentioning

confidence: 99%

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Elliptic Curve Cryptography on Constrained Microcontrollers Using Frequency Domain Arithmetic

Gulen

Baktır

2014

Computational Science and Its Applications – ICCSA 2014

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Abstract. We implemented elliptic curve cryptography in the frequency domain on the MSP430 constrained microcontroller. Our implementation of 169-bit elliptic curve cryptography (ECC) on MSP430, one of the most popular microcontrollers for wireless sensor network (WSN) nodes, performs an ECC scalar point multiplication operation, for random points, in only 1.55 ms which is similar to or faster than existing implementations. To our knowledge, this work proposes the first ever software implementation of ECC in the frequency domain on a constrained lowpower microcontroller.

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Section: Modular Multiplicationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Elliptic Curve Cryptography on Constrained Microcontrollers Using Frequency Domain Arithmetic

Gulen

Baktır

2014

Computational Science and Its Applications – ICCSA 2014

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“…Step 5, 6 in Algorithm 1). A channel selector [34] is responsible for wiring the coefficients back to their corresponding RAMs.…”

Section: B Building Blocks and Memory Control Mechanismmentioning

confidence: 99%

High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems

Chen

Mentens

Vercauteren

et al. 2015

IEEE Trans. Circuits Syst. I

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103

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Polynomial multiplication is the basic and most computationally intensive operation in ring-Learning With Errors (ring-LWE) encryption and "Somewhat" Homomorphic Encryption (SHE) cryptosystems. In this paper, the Fast Fourier Transform (FFT) with a linearithmic complexity of O(n log n), is exploited in the design of a high-speed polynomial multiplier. A constant geometry FFT datapath is used in the computation to simplify the control of the architecture. The contribution of this work is threefold. First, parameter sets which support both an efficient modular reduction design and the security requirements for ring-LWE encryption and SHE are provided. Second, a versatile pipelined architecture accompanied with an improved dataflow are proposed to obtain a high-speed polynomial multiplier. Third, the proposed architecture supports polynomial multiplications for different lengths n and moduli p. The experimental results on a Spartan-6 FPGA show that the proposed design results in a speedup of 3.5 times on average when compared with the state of the art. It performs a polynomial multiplication in the ring-LWE scheme (n = 256, p = 1049089) and the SHE scheme (n = 1024, p = 536903681) in only 6.3µs and 33.1µs, respectively.

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“…FPGA is a promising implementation technology for computationally intensive applications such as signal, image, and network processing tasks [1,2]. State-of-the-art FPGAs offer high operating frequency, unprecedented logic density and a host of other features.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient parameterized FFT architecture

Ren

Prasanna

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Recently, there has been a growing interest within the research community to improve energy efficiency. In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. Parameterized FFT architecture is proposed to identify design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize the decomposition based FFT algorithms. After empirical selection on the values of algorithm mapping parameters, an energy-performance-area trade-off design for energy efficiency is identified by varying the architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The tradeoffs between energy, area, and time are analyzed using two performance metrics: the Energy×Area×Time (EAT) composite metric and the energy efficiency (defined as the number of operations per Joule). From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N -point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.

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Low complexity and hardware-friendly spectral modular multiplication

Cited by 4 publications

References 25 publications

Elliptic Curve Cryptography on Constrained Microcontrollers Using Frequency Domain Arithmetic

Elliptic Curve Cryptography on Constrained Microcontrollers Using Frequency Domain Arithmetic

High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems

Energy efficient parameterized FFT architecture

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