Low-complexity architecture for Chase soft-decision Reed-Solomon decoding

Abstract

Soft-decision decoding of Reed-Solomon (RS) codes can achieve good coding gain by using the probability information from the channel. Among various soft-decision algorithms, the Chase algorithm has moderate performance and rational complexity and hence is usually designed for hardware implementation. Chase-type decoders, however, still have much higher complexity than that of conventional hard-decision decoders. This paper proposes a reduced-complexity Chase (RCC) algorithm and its corresponding high-speed VLSI architecture. With the developed fast and efficient decision-making scheme, the resulting hardware complexity is greatly reduced while keeping the error correction performance comparable to that of the Chase decoders. For a (255, 239) RS code, experimental results show that the proposed decoder design has at least 44.6% improvement in area-time complexity as compared to the related works. least reliable bit positions (LRBPs) {b0, b1, …, b-1} according to the soft information. For example, if l2 = 15 and b2 = 7, it indicates the position of the 7-th bit in the 15-th symbol. Note that the algorithm permits that a symbol position contains multiple bits falling in the 