Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO–OFDM CMOS transceivers

Saponara, Sergio; L'Insalata, N.E.; Fanucci, Luca

doi:10.1016/j.micpro.2008.12.001

Cited by 8 publications

(12 citation statements)

References 43 publications

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“…The architectures have been implemented by means of logic synthesis using Synopsys TM CAD tools on STMicroelectronics CMOS technologies we already used for other VLSI processing cores [36][37][38][39][40][41]: the target technologies are the 180 nm, 6 metal layers, CMOS standard-cells library and the 90 nm, 9 metal layers CMOS standard-cells library. For both technologies are available low-leakage library cells, optimized to reduce power consumption, and high-speed library cells which are optimized for higher speed (by a factor 10-20%) at the expense of an increased power consumption of the same factor.…”

Section: Cmos Synthesis Tools Libraries and Conditionsmentioning

confidence: 99%

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Saponara

2010

J Real-Time Image Proc

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The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art

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Section: Cmos Synthesis Tools Libraries and Conditionsmentioning

confidence: 99%

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Saponara

2010

J Real-Time Image Proc

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“…Samplerates of GS/s and moderate resolution, around 6 bits, are required for the ADC to be used in UWB (ultra wide band) and 60 GHz radio wireless systems [1][2][3][4][5][6][7][8][9][10]. Besides the A/D interface versus the wireless communication channel other ADC channels are required, with sample rates from few to hundreds of MS/s, to acquire the multimedia sensors data (video camera, voice acquisition systems, multi-axes accelerometers/gyro for body positioning,…).…”

Section: Introductionmentioning

confidence: 99%

Configurable array of low-complex SAR ADCs

Saponara

2011

Analog Integr Circ Sig Process

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An array of low-complex SAR ADCs, configurable in time-interleaved (TI) or parallel modes to reach 1 GS/s or to serve multiple inputs at hundreds of MS/s, is proposed in this letter. Each SAR ADC channel exploits a threshold-configuring scheme, to avoid internal DAC thus saving circuit complexity, plus a dynamic comparator which allows for power consumption scalable versus processing speed. Implementation results in 90 nm 1 V CMOS technology are presented and compared to the state of the art

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“…The IQ signals are typically digitized with a resolution of 8 bits [9]. This means that measuring EVM requires 16 bits of digital bandwidth between the tester and the device under test (DUT) just for the analog signals.…”

Section: Introductionmentioning

confidence: 99%

Built-in EVM measurement for OFDM transceivers using all-digital DFT

Yılmaz

Nassery

Ozev

et al. 2009

2009 International Test Conference

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In this paper, we present a technique to enable accurate built-in measurement of EVM for OFDM transceivers. This measurement technique only relies on the decoded bit pattern, and does not require any additional test equipment. In order to accurately predict EVM without using analog signal analysis, we intentionally code more symbols into the bit pattern in test mode, which enables the decoding of IQ signals in finer granularity. We present an innovative DFT technique to measure EVM on-chip with very little overhead. We also provide an analytical framework to determine how the DFT technique needs to be implemented. Experimental results using MATLAB simulations and hardware measurements confirm the accuracy of the proposed technique.

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Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO–OFDM CMOS transceivers

Cited by 8 publications

References 43 publications

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Configurable array of low-complex SAR ADCs

Built-in EVM measurement for OFDM transceivers using all-digital DFT

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