Low-energy multi-path adiabatic CMOS driver for low-energy system applications with large capacitive load

Abstract

This paper presents the design of a fast multi-path adi abatic CMOS driver (pr-ad). The proposed pr-ad does not uses bootstrap capacitors to minimise active area, and does not require to maintain high voltage diff erence across the junctions or the gates of output pull-up and output pull down transistors. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (lOpF), pr-ad has a higher active area (33%), but lower energy-delay product (16%) than the reference complemen tary adiabaticlbootstrap circuit (cab-lwk). Also pr-ad has very small effective input capacitance in comparison with cab-lwk because the first does not need bootstrap capaci tors connected with the input.