Low-noise and power dynamic logic circuit design based on semi-dynamic buffer

Abstract

Dynamic logic is one of the most important logic circuit structure. Due to precharge strategy, a lot of noise is introduced into the system as well as large extra power consumption. This paper proposes a novel structure for the buffer of the dynamic logic circuit. Using this proposed semi-dynamic logic buffer (SDB), the noise and power consumption in the buffer is dramatically deduced. Compared with the conventional buffer structure, the proposed one demonstrates much advantage in both power assumption and noise performance with roughly little drawback about driving ability.