Low-phase-noise self-sustaining amplifier IC with parallel capacitance cancellation for low-Q piezoelectric resonator

Kim, Hyungseup; Lee, Byeoncheol; Ko, Youngwoon; Mun, Yeongjin; Kim, Yi-Gyeong; Lee, Hyunjoong; Ko, Hyoungho

doi:10.1007/s00542-018-3830-5

Cited by 3 publications

(2 citation statements)

References 25 publications

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“…A low-power CDC based on a SAR algorithm without a pre-amplifier, one of the direct conversion schemes, has been proposed. 8 The SAR CDC without a pre-amplifier can achieve low-power consumption but is sensitive to parasitic components because the sensing capacitance is connected to a high-impedance input. 7 Recently, a high-order SC delta–sigma CDC with various schemes has been proposed to achieve high resolution.…”

Section: Introductionmentioning

confidence: 99%

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

Nam

Kim

Choi

et al. 2022

Measurement and Control

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In this paper, low-noise incremental delta–sigma analog front end (AFE) integrated circuit (IC) for capacitive microsensors is presented. A conventional capacitance-to-digital converter (CDC) mainly uses a multi-stage capacitive sensing amplified stage (CSA) and analog-to-digital converters. The multi-stage CSA is not suitable for application in various Internet of things (IoT) devices that require low power because the power consumption of the analog front-end circuit increases in proportion to the number of amplifiers and the chip area increases. So, the presented delta-sigma AFE can convert the capacitance changes to the digital codes directly. This structure can achieve a small active area and low power consumption. The delta–sigma AFE achieves low-noise and high linearity using a capacitor polarity swapping technique. The measured effective resolution is 16.2 bits, and the non-linearity is 0.05% full-scale output (FSO). The integrated circuit is implemented in a 0.18-µm standard CMOS process. All functional blocks, including the analog circuits (bandgap reference, voltage reference, and delta–sigma capacitance-to-digital converter) and digital block (accumulator and timing generator), are integrated on a chip. The proposed incremental delta–sigma AFE consumes 1.12 mW of power from a 3.3-V supply at a sampling frequency of 500 kHz and occupies a total active area of 0.42 mm2.

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Section: Introductionmentioning

confidence: 99%

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

Nam

Kim

Choi

et al. 2022

Measurement and Control

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“…Also, there are limitations in obtaining the continuous changes in Q-factor or resonant frequency. In closedloop system, self-sustained oscillator [8][9][10][11] circuit and phase-locked loop (PLL) architecture 4,12 are mainly used. Compared to the oscillator circuit, PLL architecture has better adaptability to resonators and better performance with large damped resonators.…”

Section: Introductionmentioning

confidence: 99%

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

Heo

Kim

You

et al. 2021

Measurement and Control

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This paper presents a phase-locked loop (PLL) based resonator driving integrated circuit (IC) with automatic parasitic capacitance cancellation and automatic gain control. The PLL consisting of a phase frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO) makes the driving frequency to be locked at the resonant frequency. The resonator is modeled by Butterworth–Van Dyke equivalent circuit model with motional resistance of 72.8 kΩ, capacitance of 6.19 fF, inductance of 79.4 mH, and parasitic parallel capacitance of 2.59 pF. To mitigate the magnitude and phase distortion in the resonator frequency response, it is necessary to compensate for the parasitic capacitance. The proposed automatic parasitic capacitance cancellation loop is operated in the open-loop mode. In the automatic parasitic capacitance cancellation phase, the outputs of the transimpedance amplifier (TIA) at the lower and higher frequency than the resonant frequency (VH and VL), are compared, and the programmable compensation capacitor array matches the VH and VL using binary-searched algorithm to cancel the parallel parasitic capacitance. The automatic gain control (AGC) loop keeps the oscillation at the suitable amplitude, and the AGC output can be used as a measurement of the motional resistance. The AGC loop is also digitally controlled. The proposed resonator driving IC is designed in a 0.18-μm bipolar complementary metal oxide semiconductor double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 3.2 mm2. The simulated phase noise is −61.1 dBc/Hz at 1 kHz and the quality factor ( Q-factor) is 59,590.

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Phase Locked Loop based Resonator Driving IC with Negative Charge Cancelling

Kim

Han

et al. 2020

2020 International Conference on Electronics, Information, and Communication (ICEIC)

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Low-phase-noise self-sustaining amplifier IC with parallel capacitance cancellation for low-Q piezoelectric resonator

Cited by 3 publications

References 25 publications

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

PLL-based nanoresonator driving IC with automatic parasitic capacitance cancellation and automatic gain control

Phase Locked Loop based Resonator Driving IC with Negative Charge Cancelling

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