Low-power and high speed CPL-CSA adder

Abstract

High speed, low power, area efficient adders continue to play a key role in hardware implementations of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This paper proposes a unique custom adder design in 2S0-nm CMOS technology, which is based on a combination of CPL and CS logic to obtain a fast and power/area efficient adder design. A 16 bit CPLICS adder is presented which is faster compared to the standard SQRT CS adder while significantly reducing the power and area.