Low-power buffered clock tree design

Vittal, Ashok; Marek-Sadowska, Malgorzata

doi:10.1109/43.658565

Cited by 61 publications

(29 citation statements)

References 24 publications

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“…Note also that the total FF area reduction is greater than the increase in clock buffer area. Power dissipated in the clock tree is linearly related to the number of clock sinks in a design [Vittal97]. Consequently, the design with single clock tree or triple clocks trees drives the same load and thus theoretically requires almost the same amount of energy to drive the load.…”

Section: Aes Implementationmentioning

confidence: 99%

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Gujja

Chellappa

Ramamurthy

et al. 2015

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness

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Section: Aes Implementationmentioning

confidence: 99%

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Gujja

Chellappa

Ramamurthy

et al. 2015

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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“…The most common are those based on modifying clock latencies by inserting or properly sizing clock buffers when designing the clock network [9][10][11][12][13]. For instance, [10] proposes a methodology for clock noise reduction, based on an error-driven optimization of the clock-tree latencies using supply current profiles taking timing constraints and the clock skew into account.…”

Section: Influence Of Clocking In Switching Noisementioning

confidence: 99%

Asymmetric clock driver for improved power and noise performances

Castro

Parra

Valencia

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract.-One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an important solution to reduce the switching noise generated by the global clock, with a very reduced degradation in performances and reliability. The suited sizing of clock generators and the design of asymmetric clock tree cells, show the benefits of the proposed technique, validated through a design example where a 50% of noise reduction is achieved with 10% of loss in operation frequency and no penalty, even saving, in power consumption.

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“…For some simple problems, analytic solutions are available (see, e.g., Wong 2001a, Gao and. Other problems in digital circuit design where GP plays a role include buffering and wire sizing Wong 1999, 2001a), sizing and placement (Chen et al 2000), yield maximization , Patil et al 2005, parasitic reduction (Qin and Cheng 2003), clock tree design (Vittal and Marek-Sadowska 1997), and routing (Borah et al 1997). Geometric programming has also been used for the design of nondigital circuits, e.g., analog circuits (Dawson et al 2001, Hershenson 2003, Hershenson et al 1998, Mandal and Visvanathan 2001, Vanderhaegen and Brodersen 2004, mixed-signal circuits (Colleran et al 2003, Hassibi and Hershenson 2002, Hershenson 2002, and RF (radio frequency) circuits Mohan et al 1999Mohan et al , 2000Xu et al 2004).…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Low-power buffered clock tree design

Cited by 61 publications

References 24 publications

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Asymmetric clock driver for improved power and noise performances

Digital Circuit Optimization via Geometric Programming

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