Low Power Domino Full Adder

Abstract

With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better results in terms of power, delay and power-delay product. All the simulations have been performed on 45nm technology using tanner EDA tool version 13.0.