VLSICS
 2013
DOI: 10.5121/vlsic.2013.4303
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Low Power Dual Edge - Triggered Static D Flip-Flop

Gurmohan Singh1,
Vemu Sulochana2

Abstract: This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF)

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Performance Analysis of EMTCMOS Technique-Based D Flip-Flop Design at Varied Supply Voltages and Distinct Submicron Technology

Sreenivasulu1
2019
Advances in Intelligent Systems and Computing
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Performance Analysis of EMTCMOS Technique-Based D Flip-Flop Design at Varied Supply Voltages and Distinct Submicron Technology

Sreenivasulu1
2019
Advances in Intelligent Systems and Computing
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Design and implementation of low power dual edge triggered flip-flop using GDI and TG for high speed FIR filter

Mukherjee
1
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Ghosal
2
2017
2017 Devices for Integrated Circuit (DevIC)
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Design of a D flip flop for optimization of power dissipation using GDI technique

Aparna
1
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Anandi
2
2017
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information &Amp; Communication Technology (RTEICT)
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