Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation

Sivanandam, K.; Kumar, Praveen

doi:10.1007/978-981-10-8533-8_7

Cited by 4 publications

(1 citation statement)

References 11 publications

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“…It is carried out with different specific instructions or with dedicated hardware co-processors by extending the baseline processor. The successive ASP may be specifically degraded for the execution and equipment assets [14].…”

Section: Literature Reviewmentioning

confidence: 99%

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

2023

Teh. vjesn.

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This research article proposed the reconfigurable Single Instruction Multi Data (SIMD) processor design to speed up the accelerated computing task in IoT operations. Single Instruction Multi Data models leverage the parallel real source to speed up computing accelerated tasks. It proposes the utilization of reconfigurable Kogge Stone-dependent hybrid adder structures, now referred to as KS-CPA, in which reconfiguration occurs during the addition operation. The Least Significant Bits (LSB) are processed using a carry propagate adder, while the Most Significant Bits (MSB) are computed using the Kogge Stone adder. Depending on the data width and deviceaccessible energy resources, the hybrid configuration of the adder offers the 4-bit, 8-bit, and 16-bit addition. The adder form is identified by a shift in the configuration of its Carry Look-ahead and then by a Kogge Stone Adder (KSA). Throughout the activity, the KS-CLA crossbreed configuration is used to attain the fastest speed and low energy usage. The effectiveness, including its proposed hybrid adder, is evaluated by looking at the speed, energy, and area parameters, including a suitable area use during rapid applications in which both less delay and low power adders are required. Considering these, we are structuring an IoT processor that can be reconfigured to gain from SIMD. We have demonstrated that our hybrid adder-enhanced processor saves energy up to 13% and reduces 27% latency. The proposed 16 and 32-bit adders will boost time, power, and Area Delay Product (ADP) by almost 18-24% and 13-19% respectively.

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Section: Literature Reviewmentioning

confidence: 99%

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

2023

Teh. vjesn.

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Design of Performance Enhanced Approximate Multiplier for Image Processing Applications

Sivanandam,

Sathana

2024

Communications in Computer and Information Science

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Low Power Design of Edge Detector using Static Segmented Approximate Multipliers

Sivanandam¹,

Jagadheesh²,

Bharath³

et al. 2023

2023 7th International Conference on Computing Methodologies and Communication (ICCMC)

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Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation

Cited by 4 publications

References 11 publications

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

Design of Performance Enhanced Approximate Multiplier for Image Processing Applications

Low Power Design of Edge Detector using Static Segmented Approximate Multipliers

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