Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology

Abstract

Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.