Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

Abstract

A low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain.