Low-power radix-4 quotient generator

Ercegovac, M.D.; Meng, Lu

doi:10.1109/acssc.2014.7094660

Cited by 1 publication

(1 citation statement)

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“…The multiple-bit partial quotient digits will be obtained in each recurrence cycle, and the recurrence process is realized by the multiplication of lower bit-width and subtraction of full precision [24], which improves the computational performance of the divider. However, the bit-width of the partial quotient digits generated in each recurrence cycle is related to the radix, and the calculation latency depend on the radix number.…”

Section: Introductionmentioning

confidence: 99%

An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

2021

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In this paper, a novel architecture of area-effective high-radix floating-point divider with low power consumption is proposed. By extending the principle of the standard SRT algorithm, the divider can estimate the partial quotient digits by a simpler circuit and tolerate certain calculation errors in each recurrence cycle. In addition, the accumulation of errors in the recurrence process can be eliminated automatically without additional calculation cycle. The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost. Base on the proposed architecture a single-precision floating-point divider is implemented, which has an area of 6037.20um 2 in 65nm process. The dynamic power consumption of the divider is only 0.848mW at 250MHz. Compared with other dividers reported in the literature, the area cost can be reduced by about 90% with the same computation precision and performance.INDEX TERMS High-radix, division, SRT, quotient-digits-selection.

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Section: Introductionmentioning

confidence: 99%