Low-Power Small-Area $3\times 3$ Convolution Hardware Design

Chen, Xin-Jia; Huang, Shih-Hsu

doi:10.1109/icce-taiwan49838.2020.9258026

Cited by 1 publication

(5 citation statements)

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Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Chen and Huang [ 13 ] presented the first study for the optimization of underlying 2-D convolution hardware circuit design. Note that the proposed convolver design is a revised version of the previous work [ 13 ]. The main limitation of the previous work [ 13 ] is that it uses the Baugh–Wooley algorithm [ 29 ] for signed multiplications.…”

Section: Introductionmentioning

confidence: 99%

“…Note that the proposed convolver design is a revised version of the previous work [ 13 ]. The main limitation of the previous work [ 13 ] is that it uses the Baugh–Wooley algorithm [ 29 ] for signed multiplications. Therefore, for long operands (i.e., large bit-width operands), the height of PPM is large.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, for long operands (i.e., large bit-width operands), the height of PPM is large. Different from the previous work [ 13 ], the proposed convolver design uses the modified Booth algorithm [ 30 ] for signed multiplications. Since the height of PPM is reduced by half, the proposed convolver design is more suitable for long operands.…”

Section: Introductionmentioning

confidence: 99%

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Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing

Kao

Chen

Huang

2021

Sensors

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Convolution operations have a significant influence on the overall performance of a convolutional neural network, especially in edge-computing hardware design. In this paper, we propose a low-power signed convolver hardware architecture that is well suited for low-power edge computing. The basic idea of the proposed convolver design is to combine all multipliers’ final additions and their corresponding adder tree to form a partial product matrix (PPM) and then to use the reduction tree algorithm to reduce this PPM. As a result, compared with the state-of-the-art approach, our convolver design not only saves a lot of carry propagation adders but also saves one clock cycle per convolution operation. Moreover, the proposed convolver design can be adapted for different dataflows (including input stationary dataflow, weight stationary dataflow, and output stationary dataflow). According to dataflows, two types of convolve-accumulate units are proposed to perform the accumulation of convolution results. The results show that, compared with the state-of-the-art approach, the proposed convolver design can save 15.6% power consumption. Furthermore, compared with the state-of-the-art approach, on average, the proposed convolve-accumulate units can reduce 15.7% power consumption.

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Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%