Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

Abstract

We have developed the new "Yin-Yang" feedback technology for SRAM cells. This technology is applied to sixtransistor cells and four-transistor cells, which are composed of transistors with the new DZG-SO1 structure. At the 65-nm process node, these cells can operate at 0.7 V in massproduced LSIs under real usage conditions. Max. operating speeds are 300 MHz for the six-transistor and 200 MHz for the four-transistor cell. Leakage cnrrent of the four-transistor cell is about 1/1000 that of a conventional four-transistor cell. These cells provide a SRAM menu that allows us to optimally balance the requirements of various types of SRAM in lowpower LSIs.

SRAM Read/Write Margin Enhancements Using FinFETs

“…The strong BG biasing effect can thus be leveraged [39] to optimize the performance of FinFET-based SRAMs through a dynamic adjustment of the effective cell -ratio.…”

“…Without major impact on RSNM, the pMOS load devices can be made weaker by adjusting their gate lengths. However, this technique will only yield a marginal improvement in the write margin; a much more significant improvement can be attained by lowering the supply voltage during write, while maintaining the WL voltage [39]. This is made possible by adopting a long-aspect-ratio cell layout, which is typical in today's designs for better manufacturability [2], [40]- [42], since the cell supply can be routed vertically for each column and can be exploited to break the contention between read and write optimization.…”

An Inductive-Coupling Inter-Chip Link for High-Performance and Low-Power 3D System Integration

“…That is why the inductive-coupling link does not affect SRAM operation in typical region of supply voltage while soft errors may affect. Compared with influence from device variations, it is much smaller since the difference in supply voltage of 10 mV corresponds to the difference in threshold voltage variation of 1 mV (Yamaoka et al, 2004), which is much smaller than process variation. From this measurement result, we have reached to a conclusion that inductive-coupling link can be placed near the SRAM circuits.…”

Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

“…The maximum critical path delay distribution, including both WID and D2D variations, is analyzed for three technologies: one 65-nm commercial technology and two future technology nodes 45 and 32 nm. Both the 45-and 32-nm technologies are hypothetical, and the parameters have been selected to anticipate a realistic set [10,18,[33][34][35][36].…”

“…= / for WID, D2D variations, and for critical path length n cp are given in Table 3.4. Standard deviation values are estimated by combining V th and L according to [18,[33][34][35][36], and n cp is estimated as presented in [32]. N cp D 10 4 ; finally, R D 5 in all calculations.…”